techlibs/gowin/cells_sim.v

   1 module LUT1(output F, input I0);
   2         parameter [1:0] INIT = 0;
   3         assign F = I0 ? INIT[1] : INIT[0];
   4 endmodule
   5
   6 module LUT2(output F, input I0, I1);
   7         parameter [3:0] INIT = 0;
   8         wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
   9         assign F = I0 ? s1[1] : s1[0];
  10 endmodule
  11
  12 module LUT3(output F, input I0, I1, I2);
  13         parameter [7:0] INIT = 0;
  14         wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
  15         wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  16         assign F = I0 ? s1[1] : s1[0];
  17 endmodule
  18
  19 module LUT4(output F, input I0, I1, I2, I3);
  20         parameter [15:0] INIT = 0;
  21         wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
  22         wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
  23         wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  24         assign F = I0 ? s1[1] : s1[0];
  25 endmodule
  26
  27 module DFF (output reg Q, input CLK, D);
  28         parameter [0:0] INIT = 1'b0;
  29         initial Q = INIT;
  30         always @(posedge CLK)
  31                 Q <= D;
  32 endmodule
  33
  34 module DFFN (output reg Q, input CLK, D);
  35         parameter [0:0] INIT = 1'b0;
  36         initial Q = INIT;
  37         always @(negedge CLK)
  38                 Q <= D;
  39 endmodule
  40
  41 module VCC(output V);
  42         assign V = 1;
  43 endmodule
  44
  45 module GND(output G);
  46         assign G = 0;
  47 endmodule
  48
  49 module IBUF(output O, input I);
  50         assign O = I;
  51 endmodule
  52
  53 module OBUF(output O, input I);
  54         assign O = I;
  55 endmodule
  56
  57 module GSR (input GSRI);
  58         wire GSRO = GSRI;
  59 endmodule
  60
  61 module ALU (input I0, input I1, input I3, input CIN, output COUT, output SUM);
  62    parameter [3:0] ALU_MODE = 0; // default 0 = ADD
  63    assign  {COUT, SUM} = CIN + I1 + I0;
  64 endmodule // alu
  65