techlibs/gowin/cells_sim.v

   1 module LUT1(output F, input I0);
   2         parameter [1:0] INIT = 0;
   3         assign F = I0 ? INIT[1] : INIT[0];
   4 endmodule
   5
   6 module LUT2(output F, input I0, I1);
   7         parameter [3:0] INIT = 0;
   8         wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
   9         assign F = I0 ? s1[1] : s1[0];
  10 endmodule
  11
  12 module LUT3(output F, input I0, I1, I2);
  13         parameter [7:0] INIT = 0;
  14         wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
  15         wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  16         assign F = I0 ? s1[1] : s1[0];
  17 endmodule
  18
  19 module LUT4(output F, input I0, I1, I2, I3);
  20         parameter [15:0] INIT = 0;
  21         wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
  22         wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
  23         wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  24         assign F = I0 ? s1[1] : s1[0];
  25 endmodule
  26
  27 module MUX2 (O, I0, I1, S0);
  28   input I0,I1;
  29   input S0;
  30   output O;
  31   assign O = S0 ? I1 : I0;
  32 endmodule
  33
  34 module MUX2_LUT5 (O, I0, I1, S0);
  35   input I0,I1;
  36   input S0;
  37   output O;
  38   MUX2 mux2_lut5 (O, I0, I1, S0);
  39 endmodule
  40
  41 module MUX2_LUT6 (O, I0, I1, S0);
  42   input I0,I1;
  43   input S0;
  44   output O;
  45   MUX2 mux2_lut6 (O, I0, I1, S0);
  46 endmodule
  47
  48 module MUX2_LUT7 (O, I0, I1, S0);
  49   input I0,I1;
  50   input S0;
  51   output O;
  52   MUX2 mux2_lut7 (O, I0, I1, S0);
  53 endmodule
  54
  55 module MUX2_LUT8 (O, I0, I1, S0);
  56   input I0,I1;
  57   input S0;
  58   output O;
  59   MUX2 mux2_lut8 (O, I0, I1, S0);
  60 endmodule
  61
  62 module DFF (output reg Q, input CLK, D);
  63         parameter [0:0] INIT = 1'b0;
  64         initial Q = INIT;
  65         always @(posedge CLK)
  66                 Q <= D;
  67 endmodule
  68
  69 module DFFE (output reg Q, input D, CLK, CE);
  70   parameter [0:0] INIT = 1'b0;
  71   initial Q = INIT;
  72   always @(posedge CLK) begin
  73     if (CE)
  74       Q <= D;
  75   end
  76 endmodule // DFFE (positive clock edge; clock enable)
  77
  78
  79 module DFFS (output reg Q, input D, CLK, SET);
  80   parameter [0:0] INIT = 1'b0;
  81   initial Q = INIT;
  82   always @(posedge CLK) begin
  83     if (SET)
  84       Q <= 1'b1;
  85     else
  86       Q <= D;
  87   end
  88 endmodule // DFFS (positive clock edge; synchronous set)
  89
  90
  91 module DFFSE (output reg Q, input D, CLK, CE, SET);
  92   parameter [0:0] INIT = 1'b0;
  93   initial Q = INIT;
  94   always @(posedge CLK) begin
  95     if (SET)
  96       Q <= 1'b1;
  97     else if (CE)
  98       Q <= D;
  99 end
 100 endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)
 101
 102
 103 module DFFR (output reg Q, input D, CLK, RESET);
 104   parameter [0:0] INIT = 1'b0;
 105   initial Q = INIT;
 106   always @(posedge CLK) begin
 107     if (RESET)
 108       Q <= 1'b0;
 109     else
 110       Q <= D;
 111   end
 112 endmodule // DFFR (positive clock edge; synchronous reset)
 113
 114
 115 module DFFRE (output reg Q, input D, CLK, CE, RESET);
 116   parameter [0:0] INIT = 1'b0;
 117   initial Q = INIT;
 118   always @(posedge CLK) begin
 119     if (RESET)
 120       Q <= 1'b0;
 121     else if (CE)
 122       Q <= D;
 123   end
 124 endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)
 125
 126
 127 module DFFP (output reg Q, input D, CLK, PRESET);
 128   parameter [0:0] INIT = 1'b0;
 129   initial Q = INIT;
 130   always @(posedge CLK or posedge PRESET) begin
 131     if(PRESET)
 132       Q <= 1'b1;
 133     else
 134       Q <= D;
 135   end
 136 endmodule // DFFP (positive clock edge; asynchronous preset)
 137
 138
 139 module DFFPE (output reg Q, input D, CLK, CE, PRESET);
 140   parameter [0:0] INIT = 1'b0;
 141   initial Q = INIT;
 142   always @(posedge CLK or posedge PRESET) begin
 143     if(PRESET)
 144       Q <= 1'b1;
 145     else if (CE)
 146       Q <= D;
 147   end
 148 endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)
 149
 150
 151 module DFFC (output reg Q, input D, CLK, CLEAR);
 152   parameter [0:0] INIT = 1'b0;
 153   initial Q = INIT;
 154   always @(posedge CLK or posedge CLEAR) begin
 155     if(CLEAR)
 156       Q <= 1'b0;
 157     else
 158       Q <= D;
 159   end
 160 endmodule // DFFC (positive clock edge; asynchronous clear)
 161
 162
 163 module DFFCE (output reg Q, input D, CLK, CE, CLEAR);
 164   parameter [0:0] INIT = 1'b0;
 165   initial Q = INIT;
 166   always @(posedge CLK or posedge CLEAR) begin
 167     if(CLEAR)
 168       Q <= 1'b0;
 169     else if (CE)
 170       Q <= D;
 171   end
 172 endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)
 173
 174
 175 module DFFN (output reg Q, input CLK, D);
 176         parameter [0:0] INIT = 1'b0;
 177         initial Q = INIT;
 178         always @(negedge CLK)
 179                 Q <= D;
 180 endmodule
 181
 182 module DFFNE (output reg Q, input D, CLK, CE);
 183   parameter [0:0] INIT = 1'b0;
 184   initial Q = INIT;
 185   always @(negedge CLK) begin
 186     if (CE)
 187       Q <= D;
 188   end
 189 endmodule // DFFNE (negative clock edge; clock enable)
 190
 191
 192 module DFFNS (output reg Q, input D, CLK, SET);
 193   parameter [0:0] INIT = 1'b0;
 194   initial Q = INIT;
 195   always @(negedge CLK) begin
 196     if (SET)
 197       Q <= 1'b1;
 198     else
 199       Q <= D;
 200   end
 201 endmodule // DFFNS (negative clock edge; synchronous set)
 202
 203
 204 module DFFNSE (output reg Q, input D, CLK, CE, SET);
 205   parameter [0:0] INIT = 1'b0;
 206   initial Q = INIT;
 207   always @(negedge CLK) begin
 208     if (SET)
 209       Q <= 1'b1;
 210     else if (CE)
 211       Q <= D;
 212 end
 213 endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)
 214
 215
 216 module DFFNR (output reg Q, input D, CLK, RESET);
 217   parameter [0:0] INIT = 1'b0;
 218   initial Q = INIT;
 219   always @(negedge CLK) begin
 220     if (RESET)
 221       Q <= 1'b0;
 222     else
 223       Q <= D;
 224   end
 225 endmodule // DFFNR (negative clock edge; synchronous reset)
 226
 227
 228 module DFFNRE (output reg Q, input D, CLK, CE, RESET);
 229   parameter [0:0] INIT = 1'b0;
 230   initial Q = INIT;
 231   always @(negedge CLK) begin
 232     if (RESET)
 233       Q <= 1'b0;
 234     else if (CE)
 235       Q <= D;
 236   end
 237 endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)
 238
 239
 240 module DFFNP (output reg Q, input D, CLK, PRESET);
 241   parameter [0:0] INIT = 1'b0;
 242   initial Q = INIT;
 243   always @(negedge CLK or posedge PRESET) begin
 244     if(PRESET)
 245       Q <= 1'b1;
 246     else
 247       Q <= D;
 248   end
 249 endmodule // DFFNP (negative clock edge; asynchronous preset)
 250
 251
 252 module DFFNPE (output reg Q, input D, CLK, CE, PRESET);
 253   parameter [0:0] INIT = 1'b0;
 254   initial Q = INIT;
 255   always @(negedge CLK or posedge PRESET) begin
 256     if(PRESET)
 257       Q <= 1'b1;
 258     else if (CE)
 259       Q <= D;
 260   end
 261 endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)
 262
 263
 264 module DFFNC (output reg Q, input D, CLK, CLEAR);
 265   parameter [0:0] INIT = 1'b0;
 266   initial Q = INIT;
 267   always @(negedge CLK or posedge CLEAR) begin
 268     if(CLEAR)
 269       Q <= 1'b0;
 270     else
 271       Q <= D;
 272   end
 273 endmodule // DFFNC (negative clock edge; asynchronous clear)
 274
 275
 276 module DFFNCE (output reg Q, input D, CLK, CE, CLEAR);
 277   parameter [0:0] INIT = 1'b0;
 278   initial Q = INIT;
 279   always @(negedge CLK or posedge CLEAR) begin
 280     if(CLEAR)
 281       Q <= 1'b0;
 282     else if (CE)
 283       Q <= D;
 284   end
 285 endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)
 286
 287 // TODO add more DFF sim cells
 288
 289 module VCC(output V);
 290         assign V = 1;
 291 endmodule
 292
 293 module GND(output G);
 294         assign G = 0;
 295 endmodule
 296
 297 module IBUF(output O, input I);
 298         assign O = I;
 299 endmodule
 300
 301 module OBUF(output O, input I);
 302         assign O = I;
 303 endmodule
 304
 305 module TBUF (O, I, OEN);
 306   input I, OEN;
 307   output O;
 308   assign O = OEN ? I : 1'bz;
 309 endmodule
 310
 311 module IOBUF (O, IO, I, OEN);
 312   input I,OEN;
 313   output O;
 314   inout IO;
 315   assign IO = OEN ? I : 1'bz;
 316   assign I = IO;
 317 endmodule
 318
 319 module GSR (input GSRI);
 320         wire GSRO = GSRI;
 321 endmodule
 322
 323 module ALU (SUM, COUT, I0, I1, I3, CIN);
 324
 325 input I0;
 326 input I1;
 327 input I3;
 328 input CIN;
 329 output SUM;
 330 output COUT;
 331
 332 localparam ADD = 0;
 333 localparam SUB = 1;
 334 localparam ADDSUB = 2;
 335 localparam NE = 3;
 336 localparam GE = 4;
 337 localparam LE = 5;
 338 localparam CUP = 6;
 339 localparam CDN = 7;
 340 localparam CUPCDN = 8;
 341 localparam MULT = 9;
 342
 343 parameter ALU_MODE = 0;
 344
 345 reg S, C;
 346
 347 assign SUM = S ^ CIN;
 348 assign COUT = S? CIN : C;
 349
 350 always @* begin
 351         case (ALU_MODE)
 352                 ADD: begin
 353                         S = I0 ^ I1;
 354                         C = I0;
 355                 end
 356                 SUB: begin
 357                         S = I0 ^ ~I1;
 358                         C = I0;
 359                 end
 360                 ADDSUB: begin
 361                         S = I3? I0 ^ I1 : I0 ^ ~I1;
 362                         C = I0;
 363                 end
 364                 NE: begin
 365                         S = I0 ^ ~I1;
 366                         C = 1'b1;
 367                 end
 368                 GE: begin
 369                         S = I0 ^ ~I1;
 370                         C = I0;
 371                 end
 372                 LE: begin
 373                         S = ~I0 ^ I1;
 374                         C = I1;
 375                 end
 376                 CUP: begin
 377                         S = I0;
 378                         C = 1'b0;
 379                 end
 380                 CDN: begin
 381                         S = ~I0;
 382                         C = 1'b1;
 383                 end
 384                 CUPCDN: begin
 385                         S = I3? I0 : ~I0;
 386                         C = I0;
 387                 end
 388                 MULT: begin
 389                         S = I0 & I1;
 390                         C = I0 & I1;
 391                 end
 392         endcase
 393 end
 394
 395 endmodule
 396
 397
 398 module RAM16S4 (DO, DI, AD, WRE, CLK);
 399    parameter WIDTH  = 4;
 400    parameter INIT_0 = 16'h0000;
 401    parameter INIT_1 = 16'h0000;
 402    parameter INIT_2 = 16'h0000;
 403    parameter INIT_3 = 16'h0000;
 404
 405    input  [WIDTH-1:0] AD;
 406    input  [WIDTH-1:0] DI;
 407    output [WIDTH-1:0] DO;
 408    input              CLK;
 409    input              WRE;
 410
 411    reg [15:0]       mem0, mem1, mem2, mem3;
 412
 413    initial begin
 414       mem0 = INIT_0;
 415       mem1 = INIT_1;
 416       mem2 = INIT_2;
 417       mem3 = INIT_3;
 418    end
 419
 420    assign       DO[0] = mem0[AD];
 421    assign       DO[1] = mem1[AD];
 422    assign       DO[2] = mem2[AD];
 423    assign       DO[3] = mem3[AD];
 424
 425    always @(posedge CLK) begin
 426       if (WRE) begin
 427          mem0[AD] <= DI[0];
 428          mem1[AD] <= DI[1];
 429          mem2[AD] <= DI[2];
 430          mem3[AD] <= DI[3];
 431       end
 432    end
 433
 434 endmodule // RAM16S4
 435
 436
 437 (* blackbox *)
 438 module SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);
 439 //1'b0: Bypass mode; 1'b1 Pipeline mode
 440 parameter READ_MODE = 1'b0;
 441 parameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32
 442 parameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32
 443 parameter BLK_SEL = 3'b000;
 444 parameter RESET_MODE = "SYNC";
 445 parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 446 parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 447 parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 448 parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 449 parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 450 parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 451 parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 452 parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 453 parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 454 parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 455 parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 456 parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 457 parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 458 parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 459 parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 460 parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 461 parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 462 parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 463 parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 464 parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 465 parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 466 parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 467 parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 468 parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 469 parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 470 parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 471 parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 472 parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 473 parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 474 parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 475 parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 476 parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 477 parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 478 parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 479 parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 480 parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 481 parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 482 parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 483 parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 484 parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 485 parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 486 parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 487 parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 488 parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 489 parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 490 parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 491 parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 492 parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 493 parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 494 parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 495 parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 496 parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 497 parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 498 parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 499 parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 500 parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 501 parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 502 parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 503 parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 504 parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 505 parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 506 parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 507 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 508 parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 509
 510 input CLKA, CEA, CLKB, CEB;
 511 input OCE; // clock enable of memory output register
 512 input RESETA, RESETB; // resets output registers, not memory contents
 513 input WREA, WREB; // 1'b0: read enabled; 1'b1: write enabled
 514 input [13:0] ADA, ADB;
 515 input [31:0] DI;
 516 input [2:0] BLKSEL;
 517 output [31:0] DO;
 518
 519 endmodule
 520