techlibs/gowin/cells_sim.v

   1 module LUT1(output F, input I0);
   2         parameter [1:0] INIT = 0;
   3         assign F = I0 ? INIT[1] : INIT[0];
   4 endmodule
   5
   6 module LUT2(output F, input I0, I1);
   7         parameter [3:0] INIT = 0;
   8         wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
   9         assign F = I0 ? s1[1] : s1[0];
  10 endmodule
  11
  12 module LUT3(output F, input I0, I1, I2);
  13         parameter [7:0] INIT = 0;
  14         wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
  15         wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  16         assign F = I0 ? s1[1] : s1[0];
  17 endmodule
  18
  19 module LUT4(output F, input I0, I1, I2, I3);
  20         parameter [15:0] INIT = 0;
  21         wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
  22         wire [ 3: 0] s2 = I2 ?   s3[ 7: 4] :   s3[ 3: 0];
  23         wire [ 1: 0] s1 = I1 ?   s2[ 3: 2] :   s2[ 1: 0];
  24         assign F = I0 ? s1[1] : s1[0];
  25 endmodule
  26
  27 module DFF (output reg Q, input CLK, D);
  28         parameter [0:0] INIT = 1'b0;
  29         initial Q = INIT;
  30         always @(posedge CLK)
  31                 Q <= D;
  32 endmodule
  33
  34 module DFFN (output reg Q, input CLK, D);
  35         parameter [0:0] INIT = 1'b0;
  36         initial Q = INIT;
  37         always @(negedge CLK)
  38                 Q <= D;
  39 endmodule
  40
  41 module DFFR (output reg Q, input D, CLK, RESET);
  42         parameter [0:0] INIT = 1'b0;
  43         initial Q = INIT;
  44         always @(posedge CLK) begin
  45         if (RESET)
  46                 Q <= 1'b0;
  47         else
  48                 Q <= D;
  49         end
  50 endmodule // DFFR (positive clock edge; synchronous reset)
  51
  52 module VCC(output V);
  53         assign V = 1;
  54 endmodule
  55
  56 module GND(output G);
  57         assign G = 0;
  58 endmodule
  59
  60 module IBUF(output O, input I);
  61         assign O = I;
  62 endmodule
  63
  64 module OBUF(output O, input I);
  65         assign O = I;
  66 endmodule
  67
  68 module GSR (input GSRI);
  69         wire GSRO = GSRI;
  70 endmodule
  71
  72 module ALU (input I0, input I1, input I3, input CIN, output COUT, output SUM);
  73    parameter [3:0] ALU_MODE = 0; // default 0 = ADD
  74    assign  {COUT, SUM} = CIN + I1 + I0;
  75 endmodule // alu
  76
  77 module RAM16S4 (DO, DI, AD, WRE, CLK);
  78    parameter WIDTH  = 4;
  79    parameter INIT_0 = 16'h0000;
  80    parameter INIT_1 = 16'h0000;
  81    parameter INIT_2 = 16'h0000;
  82    parameter INIT_3 = 16'h0000;
  83
  84    input  [WIDTH-1:0] AD;
  85    input  [WIDTH-1:0] DI;
  86    output [WIDTH-1:0] DO;
  87    input              CLK;
  88    input              WRE;
  89
  90    reg [15:0]       mem0, mem1, mem2, mem3;
  91
  92    initial begin
  93       mem0 = INIT_0;
  94       mem1 = INIT_1;
  95       mem2 = INIT_2;
  96       mem3 = INIT_3;
  97    end
  98
  99    assign       DO[0] = mem0[AD];
 100    assign       DO[1] = mem1[AD];
 101    assign       DO[2] = mem2[AD];
 102    assign       DO[3] = mem3[AD];
 103
 104    always @(posedge CLK) begin
 105       if (WRE) begin
 106          mem0[AD] <= DI[0];
 107          mem1[AD] <= DI[1];
 108          mem2[AD] <= DI[2];
 109          mem3[AD] <= DI[3];
 110       end
 111    end
 112
 113 endmodule // RAM16S4
 114
 115
 116 (* blackbox *)
 117 module SDP (DO, DI, BLKSEL, ADA, ADB, WREA, WREB, CLKA, CLKB, CEA, CEB, OCE, RESETA, RESETB);
 118 //1'b0: Bypass mode; 1'b1 Pipeline mode
 119 parameter READ_MODE = 1'b0;
 120 parameter BIT_WIDTH_0 = 32; // 1, 2, 4, 8, 16, 32
 121 parameter BIT_WIDTH_1 = 32; // 1, 2, 4, 8, 16, 32
 122 parameter BLK_SEL = 3'b000;
 123 parameter RESET_MODE = "SYNC";
 124 parameter INIT_RAM_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 125 parameter INIT_RAM_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 126 parameter INIT_RAM_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 127 parameter INIT_RAM_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 128 parameter INIT_RAM_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 129 parameter INIT_RAM_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 130 parameter INIT_RAM_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 131 parameter INIT_RAM_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 132 parameter INIT_RAM_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 133 parameter INIT_RAM_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 134 parameter INIT_RAM_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 135 parameter INIT_RAM_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 136 parameter INIT_RAM_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 137 parameter INIT_RAM_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 138 parameter INIT_RAM_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 139 parameter INIT_RAM_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 140 parameter INIT_RAM_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 141 parameter INIT_RAM_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 142 parameter INIT_RAM_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 143 parameter INIT_RAM_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 144 parameter INIT_RAM_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 145 parameter INIT_RAM_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 146 parameter INIT_RAM_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 147 parameter INIT_RAM_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 148 parameter INIT_RAM_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 149 parameter INIT_RAM_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 150 parameter INIT_RAM_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 151 parameter INIT_RAM_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 152 parameter INIT_RAM_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 153 parameter INIT_RAM_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 154 parameter INIT_RAM_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 155 parameter INIT_RAM_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 156 parameter INIT_RAM_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 157 parameter INIT_RAM_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 158 parameter INIT_RAM_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 159 parameter INIT_RAM_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 160 parameter INIT_RAM_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 161 parameter INIT_RAM_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 162 parameter INIT_RAM_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 163 parameter INIT_RAM_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 164 parameter INIT_RAM_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 165 parameter INIT_RAM_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 166 parameter INIT_RAM_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 167 parameter INIT_RAM_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 168 parameter INIT_RAM_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 169 parameter INIT_RAM_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 170 parameter INIT_RAM_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 171 parameter INIT_RAM_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 172 parameter INIT_RAM_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 173 parameter INIT_RAM_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 174 parameter INIT_RAM_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 175 parameter INIT_RAM_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 176 parameter INIT_RAM_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 177 parameter INIT_RAM_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 178 parameter INIT_RAM_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 179 parameter INIT_RAM_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 180 parameter INIT_RAM_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 181 parameter INIT_RAM_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 182 parameter INIT_RAM_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 183 parameter INIT_RAM_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 184 parameter INIT_RAM_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 185 parameter INIT_RAM_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 186 parameter INIT_RAM_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 187 parameter INIT_RAM_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 188
 189 input CLKA, CEA, CLKB, CEB;
 190 input OCE; // clock enable of memory output register
 191 input RESETA, RESETB; // resets output registers, not memory contents
 192 input WREA, WREB; // 1'b0: read enabled; 1'b1: write enabled
 193 input [13:0] ADA, ADB;
 194 input [31:0] DI;
 195 input [2:0] BLKSEL;
 196 output [31:0] DO;
 197
 198 endmodule
 199