Merge https://github.com/bogdanvuk/yosys into bogdanvuk/opt_share
[yosys.git] / techlibs / gowin / drams_map.v
1 module \$__GW1NR_RAM16S4 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
2 parameter CFG_ABITS = 4;
3 parameter CFG_DBITS = 4;
4
5 parameter [63:0] INIT = 64'bx;
6 input CLK1;
7
8 input [CFG_ABITS-1:0] A1ADDR;
9 output [CFG_DBITS-1:0] A1DATA;
10 input A1EN;
11
12 input [CFG_ABITS-1:0] B1ADDR;
13 input [CFG_DBITS-1:0] B1DATA;
14 input B1EN;
15
16 `include "brams_init3.vh"
17
18 RAM16S4
19 #(.INIT_0(INIT_0),
20 .INIT_1(INIT_1),
21 .INIT_2(INIT_2),
22 .INIT_3(INIT_3))
23 _TECHMAP_REPLACE_
24 (.AD(B1ADDR),
25 .DI(B1DATA),
26 .DO(A1DATA),
27 .CLK(CLK1),
28 .WRE(B1EN));
29
30
31 endmodule