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abc9: generate $abc9_holes design instead of <name>$holes
[yosys.git]
/
techlibs
/
gowin
/
lutrams.txt
1
bram $__GW1NR_RAM16S4
2
init 1
3
abits 4
4
dbits 4
5
groups 2
6
ports 1 1
7
wrmode 0 1
8
enable 0 1
9
transp 0 1
10
clocks 0 1
11
clkpol 0 1
12
endbram
13
14
match $__GW1NR_RAM16S4
15
make_outreg
16
min wports 1
17
endmatch