Harmonize BRAM/LUTRAM descriptions across all of Yosys.
[yosys.git] / techlibs / gowin / synth_gowin.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
24
25 USING_YOSYS_NAMESPACE
26 PRIVATE_NAMESPACE_BEGIN
27
28 struct SynthGowinPass : public ScriptPass
29 {
30 SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { }
31
32 void help() YS_OVERRIDE
33 {
34 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
35 log("\n");
36 log(" synth_gowin [options]\n");
37 log("\n");
38 log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
39 log("\n");
40 log(" -top <module>\n");
41 log(" use the specified module as top module (default='top')\n");
42 log("\n");
43 log(" -vout <file>\n");
44 log(" write the design to the specified Verilog netlist file. writing of an\n");
45 log(" output file is omitted if this parameter is not specified.\n");
46 log("\n");
47 log(" -run <from_label>:<to_label>\n");
48 log(" only run the commands between the labels (see below). an empty\n");
49 log(" from label is synonymous to 'begin', and empty to label is\n");
50 log(" synonymous to the end of the command list.\n");
51 log("\n");
52 log(" -nodffe\n");
53 log(" do not use flipflops with CE in output netlist\n");
54 log("\n");
55 log(" -nobram\n");
56 log(" do not use BRAM cells in output netlist\n");
57 log("\n");
58 log(" -nolutram\n");
59 log(" do not use distributed RAM cells in output netlist\n");
60 log("\n");
61 log(" -noflatten\n");
62 log(" do not flatten design before synthesis\n");
63 log("\n");
64 log(" -retime\n");
65 log(" run 'abc' with -dff option\n");
66 log("\n");
67 log(" -nowidelut\n");
68 log(" do not use muxes to implement LUTs larger than LUT4s\n");
69 log("\n");
70 log(" -noiopads\n");
71 log(" do not emit IOB at top level ports\n");
72 log("\n");
73 log(" -abc9\n");
74 log(" use new ABC9 flow (EXPERIMENTAL)\n");
75 log("\n");
76 log("\n");
77 log("The following commands are executed by this synthesis command:\n");
78 help_script();
79 log("\n");
80 }
81
82 string top_opt, vout_file;
83 bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads;
84
85 void clear_flags() YS_OVERRIDE
86 {
87 top_opt = "-auto-top";
88 vout_file = "";
89 retime = false;
90 flatten = true;
91 nobram = false;
92 nodffe = false;
93 nolutram = false;
94 nowidelut = false;
95 abc9 = false;
96 noiopads = false;
97 }
98
99 void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
100 {
101 string run_from, run_to;
102 clear_flags();
103
104 size_t argidx;
105 for (argidx = 1; argidx < args.size(); argidx++)
106 {
107 if (args[argidx] == "-top" && argidx+1 < args.size()) {
108 top_opt = "-top " + args[++argidx];
109 continue;
110 }
111 if (args[argidx] == "-vout" && argidx+1 < args.size()) {
112 vout_file = args[++argidx];
113 continue;
114 }
115 if (args[argidx] == "-run" && argidx+1 < args.size()) {
116 size_t pos = args[argidx+1].find(':');
117 if (pos == std::string::npos)
118 break;
119 run_from = args[++argidx].substr(0, pos);
120 run_to = args[argidx].substr(pos+1);
121 continue;
122 }
123 if (args[argidx] == "-retime") {
124 retime = true;
125 continue;
126 }
127 if (args[argidx] == "-nobram") {
128 nobram = true;
129 continue;
130 }
131 if (args[argidx] == "-nolutram" || /*deprecated*/args[argidx] == "-nodram") {
132 nolutram = true;
133 continue;
134 }
135 if (args[argidx] == "-nodffe") {
136 nodffe = true;
137 continue;
138 }
139 if (args[argidx] == "-noflatten") {
140 flatten = false;
141 continue;
142 }
143 if (args[argidx] == "-nowidelut") {
144 nowidelut = true;
145 continue;
146 }
147 if (args[argidx] == "-abc9") {
148 abc9 = true;
149 continue;
150 }
151 if (args[argidx] == "-noiopads") {
152 noiopads = true;
153 continue;
154 }
155 break;
156 }
157 extra_args(args, argidx, design);
158
159 if (!design->full_selection())
160 log_cmd_error("This command only operates on fully selected designs!\n");
161
162 log_header(design, "Executing SYNTH_GOWIN pass.\n");
163 log_push();
164
165 run_script(design, run_from, run_to);
166
167 log_pop();
168 }
169
170 void script() YS_OVERRIDE
171 {
172 if (check_label("begin"))
173 {
174 run("read_verilog -lib +/gowin/cells_sim.v");
175 run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
176 }
177
178 if (flatten && check_label("flatten", "(unless -noflatten)"))
179 {
180 run("proc");
181 run("flatten");
182 run("tribuf -logic");
183 run("deminout");
184 }
185
186 if (check_label("coarse"))
187 {
188 run("synth -run coarse");
189 }
190
191 if (!nobram && check_label("map_bram", "(skip if -nobram)"))
192 {
193 run("memory_bram -rules +/gowin/brams.txt");
194 run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
195 }
196
197 if (!nolutram && check_label("map_lutram", "(skip if -nolutram)"))
198 {
199 run("memory_bram -rules +/gowin/lutrams.txt");
200 run("techmap -map +/gowin/lutrams_map.v");
201 run("determine_init");
202 }
203
204 if (check_label("map_ffram"))
205 {
206 run("opt -fast -mux_undef -undriven -fine");
207 run("memory_map");
208 run("opt -undriven -fine");
209 }
210
211 if (check_label("map_gates"))
212 {
213 run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
214 run("techmap -map +/techmap.v");
215 if (retime || help_mode)
216 run("abc -dff", "(only if -retime)");
217 run("splitnets");
218 }
219
220 if (check_label("map_ffs"))
221 {
222 run("dffsr2dff");
223 run("dff2dffs -match-init");
224 run("opt_clean");
225 if (!nodffe)
226 run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
227 run("techmap -map +/gowin/cells_map.v");
228 run("opt_expr -mux_undef");
229 run("simplemap");
230 }
231
232 if (check_label("map_luts"))
233 {
234 if (nowidelut && abc9) {
235 run("abc9 -lut 4");
236 } else if (nowidelut && !abc9) {
237 run("abc -lut 4");
238 } else if (!nowidelut && abc9) {
239 run("abc9 -lut 4:8");
240 } else if (!nowidelut && !abc9) {
241 run("abc -lut 4:8");
242 }
243 run("clean");
244 }
245
246 if (check_label("map_cells"))
247 {
248 run("techmap -map +/gowin/cells_map.v");
249 run("setundef -undriven -params -zero");
250 run("hilomap -singleton -hicell VCC V -locell GND G");
251 if (!noiopads || help_mode)
252 run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O "
253 "-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)");
254 run("clean");
255 }
256
257 if (check_label("check"))
258 {
259 run("hierarchy -check");
260 run("stat");
261 run("check -noinit");
262 }
263
264 if (check_label("vout"))
265 {
266 if (!vout_file.empty() || help_mode)
267 run(stringf("write_verilog -decimal -attr2comment -defparam -renameprefix gen %s",
268 help_mode ? "<file-name>" : vout_file.c_str()));
269 }
270 }
271 } SynthGowinPass;
272
273 PRIVATE_NAMESPACE_END