techlibs/gowin/synth_gowin.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 struct SynthGowinPass : public ScriptPass
  29 {
  30         SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { }
  31
  32         void help() YS_OVERRIDE
  33         {
  34                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  35                 log("\n");
  36                 log("    synth_gowin [options]\n");
  37                 log("\n");
  38                 log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n");
  39                 log("\n");
  40                 log("    -top <module>\n");
  41                 log("        use the specified module as top module (default='top')\n");
  42                 log("\n");
  43                 log("    -vout <file>\n");
  44                 log("        write the design to the specified Verilog netlist file. writing of an\n");
  45                 log("        output file is omitted if this parameter is not specified.\n");
  46                 log("\n");
  47                 log("    -run <from_label>:<to_label>\n");
  48                 log("        only run the commands between the labels (see below). an empty\n");
  49                 log("        from label is synonymous to 'begin', and empty to label is\n");
  50                 log("        synonymous to the end of the command list.\n");
  51                 log("\n");
  52                 log("    -nodffe\n");
  53                 log("        do not use flipflops with CE in output netlist\n");
  54                 log("\n");
  55                 log("    -nobram\n");
  56                 log("        do not use BRAM cells in output netlist\n");
  57                 log("\n");
  58                 log("    -nodram\n");
  59                 log("        do not use distributed RAM cells in output netlist\n");
  60                 log("\n");
  61                 log("    -noflatten\n");
  62                 log("        do not flatten design before synthesis\n");
  63                 log("\n");
  64                 log("    -retime\n");
  65                 log("        run 'abc' with -dff option\n");
  66                 log("\n");
  67                 log("\n");
  68                 log("The following commands are executed by this synthesis command:\n");
  69                 help_script();
  70                 log("\n");
  71         }
  72
  73         string top_opt, vout_file;
  74         bool retime, nobram, nodram, flatten, nodffe;
  75
  76         void clear_flags() YS_OVERRIDE
  77         {
  78                 top_opt = "-auto-top";
  79                 vout_file = "";
  80                 retime = false;
  81                 flatten = true;
  82                 nobram = false;
  83                 nodffe = false;
  84                 nodram = false;
  85         }
  86
  87         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  88         {
  89                 string run_from, run_to;
  90                 clear_flags();
  91
  92                 size_t argidx;
  93                 for (argidx = 1; argidx < args.size(); argidx++)
  94                 {
  95                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
  96                                 top_opt = "-top " + args[++argidx];
  97                                 continue;
  98                         }
  99                         if (args[argidx] == "-vout" && argidx+1 < args.size()) {
 100                                 vout_file = args[++argidx];
 101                                 continue;
 102                         }
 103                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 104                                 size_t pos = args[argidx+1].find(':');
 105                                 if (pos == std::string::npos)
 106                                         break;
 107                                 run_from = args[++argidx].substr(0, pos);
 108                                 run_to = args[argidx].substr(pos+1);
 109                                 continue;
 110                         }
 111                         if (args[argidx] == "-retime") {
 112                                 retime = true;
 113                                 continue;
 114                         }
 115                         if (args[argidx] == "-nobram") {
 116                                 nobram = true;
 117                                 continue;
 118                         }
 119                         if (args[argidx] == "-nodram") {
 120                                 nodram = true;
 121                                 continue;
 122                         }
 123                         if (args[argidx] == "-nodffe") {
 124                                 nodffe = true;
 125                                 continue;
 126                         }
 127                         if (args[argidx] == "-noflatten") {
 128                                 flatten = false;
 129                                 continue;
 130                         }
 131                         break;
 132                 }
 133                 extra_args(args, argidx, design);
 134
 135                 if (!design->full_selection())
 136                         log_cmd_error("This command only operates on fully selected designs!\n");
 137
 138                 log_header(design, "Executing SYNTH_GOWIN pass.\n");
 139                 log_push();
 140
 141                 run_script(design, run_from, run_to);
 142
 143                 log_pop();
 144         }
 145
 146         void script() YS_OVERRIDE
 147         {
 148                 if (check_label("begin"))
 149                 {
 150                         run("read_verilog -lib +/gowin/cells_sim.v");
 151                         run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 152                 }
 153
 154                 if (flatten && check_label("flatten", "(unless -noflatten)"))
 155                 {
 156                         run("proc");
 157                         run("flatten");
 158                         run("tribuf -logic");
 159                         run("deminout");
 160                 }
 161
 162                 if (check_label("coarse"))
 163                 {
 164                         run("synth -run coarse");
 165                 }
 166
 167                 if (!nobram && check_label("bram", "(skip if -nobram)"))
 168                 {
 169                         run("memory_bram -rules +/gowin/bram.txt");
 170                         run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v");
 171                 }
 172
 173                 if (!nodram && check_label("dram", "(skip if -nodram)"))
 174                 {
 175                         run("memory_bram -rules +/gowin/dram.txt");
 176                         run("techmap -map +/gowin/drams_map.v");
 177                         run("determine_init");
 178                 }
 179
 180                 if (check_label("fine"))
 181                 {
 182                         run("opt -fast -mux_undef -undriven -fine");
 183                         run("memory_map");
 184                         run("opt -undriven -fine");
 185                         run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
 186                         run("techmap -map +/techmap.v");
 187                         if (retime || help_mode)
 188                                 run("abc -dff", "(only if -retime)");
 189                 }
 190
 191                 if (check_label("map_ffs"))
 192                 {
 193                         run("dffsr2dff");
 194                         run("dff2dffs");
 195                         run("opt_clean");
 196                         if (!nodffe)
 197                                 run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
 198                         run("techmap -map +/gowin/cells_map.v");
 199                         run("opt_expr -mux_undef");
 200                         run("simplemap");
 201                 }
 202
 203                 if (check_label("map_luts"))
 204                 {
 205                         run("abc -lut 4");
 206                         run("clean");
 207                 }
 208
 209                 if (check_label("map_cells"))
 210                 {
 211                         run("techmap -map +/gowin/cells_map.v");
 212                         run("hilomap -hicell VCC V -locell GND G");
 213                         run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)");
 214                         run("dffinit  -ff DFF Q INIT");
 215                         run("clean");
 216
 217                 }
 218
 219                 if (check_label("check"))
 220                 {
 221                         run("hierarchy -check");
 222                         run("stat");
 223                         run("check -noinit");
 224                 }
 225
 226                 if (check_label("vout"))
 227                 {
 228                         if (!vout_file.empty() || help_mode)
 229                                 run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix gen %s",
 230                                                 help_mode ? "<file-name>" : vout_file.c_str()));
 231                 }
 232         }
 233 } SynthGowinPass;
 234
 235 PRIVATE_NAMESPACE_END