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Try new LUT delays
[yosys.git]
/
techlibs
/
greenpak4
/
cells_latch.v
1
module $_DLATCH_P_(input E, input D, output Q);
2
GP_DLATCH _TECHMAP_REPLACE_ (
3
.D(D),
4
.nCLK(!E),
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.Q(Q)
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);
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endmodule
8
9
module $_DLATCH_N_(input E, input D, output Q);
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GP_DLATCH _TECHMAP_REPLACE_ (
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.D(D),
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.nCLK(E),
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.Q(Q)
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);
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endmodule