techlibs/greenpak4/cells_sim.v

   1 module GP_2LUT(input IN0, IN1, output OUT);
   2         parameter [3:0] INIT = 0;
   3         assign OUT = INIT[{IN1, IN0}];
   4 endmodule
   5
   6 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   7         parameter [7:0] INIT = 0;
   8         assign OUT = INIT[{IN2, IN1, IN0}];
   9 endmodule
  10
  11 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  12         parameter [15:0] INIT = 0;
  13         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  14 endmodule
  15
  16 module GP_ABUF(input wire IN, output wire OUT);
  17
  18         assign OUT = IN;
  19
  20 endmodule
  21
  22 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  23
  24         parameter BANDWIDTH = "HIGH";
  25         parameter VIN_ATTEN = 1;
  26         parameter VIN_ISRC_EN = 0;
  27         parameter HYSTERESIS = 0;
  28
  29         initial OUT = 0;
  30
  31         //cannot simulate mixed signal IP
  32
  33 endmodule
  34
  35 module GP_BANDGAP(output reg OK, output reg VOUT);
  36         parameter AUTO_PWRDN = 1;
  37         parameter CHOPPER_EN = 1;
  38         parameter OUT_DELAY = 100;
  39
  40         //cannot simulate mixed signal IP
  41
  42 endmodule
  43
  44 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  45
  46         parameter RESET_MODE    = "RISING";
  47
  48         parameter COUNT_TO              = 8'h1;
  49         parameter CLKIN_DIVIDE  = 1;
  50
  51         //more complex hard IP blocks are not supported for simulation yet
  52
  53         reg[7:0] count = COUNT_TO;
  54
  55         //Combinatorially output whenever we wrap low
  56         always @(*) begin
  57                 OUT <= (count == 8'h0);
  58         end
  59
  60         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  61         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  62         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  63         always @(posedge CLK) begin
  64
  65                 count           <= count - 1'd1;
  66
  67                 if(count == 0)
  68                         count   <= COUNT_MAX;
  69
  70                 /*
  71                 if((RESET_MODE == "RISING") && RST)
  72                         count   <= 0;
  73                 if((RESET_MODE == "FALLING") && !RST)
  74                         count   <= 0;
  75                 if((RESET_MODE == "BOTH") && RST)
  76                         count   <= 0;
  77                 */
  78         end
  79
  80 endmodule
  81
  82 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  83
  84         parameter RESET_MODE    = "RISING";
  85
  86         parameter COUNT_TO              = 14'h1;
  87         parameter CLKIN_DIVIDE  = 1;
  88
  89         //more complex hard IP blocks are not supported for simulation yet
  90
  91 endmodule
  92
  93 module GP_DFF(input D, CLK, output reg Q);
  94         parameter [0:0] INIT = 1'bx;
  95         initial Q = INIT;
  96         always @(posedge CLK) begin
  97                 Q <= D;
  98         end
  99 endmodule
 100
 101 module GP_DFFR(input D, CLK, nRST, output reg Q);
 102         parameter [0:0] INIT = 1'bx;
 103         initial Q = INIT;
 104         always @(posedge CLK, negedge nRST) begin
 105                 if (!nRST)
 106                         Q <= 1'b0;
 107                 else
 108                         Q <= D;
 109         end
 110 endmodule
 111
 112 module GP_DFFS(input D, CLK, nSET, output reg Q);
 113         parameter [0:0] INIT = 1'bx;
 114         initial Q = INIT;
 115         always @(posedge CLK, negedge nSET) begin
 116                 if (!nSET)
 117                         Q <= 1'b1;
 118                 else
 119                         Q <= D;
 120         end
 121 endmodule
 122
 123 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 124         parameter [0:0] INIT = 1'bx;
 125         parameter [0:0] SRMODE = 1'bx;
 126         initial Q = INIT;
 127         always @(posedge CLK, negedge nSR) begin
 128                 if (!nSR)
 129                         Q <= SRMODE;
 130                 else
 131                         Q <= D;
 132         end
 133 endmodule
 134
 135 module GP_INV(input IN, output OUT);
 136         assign OUT = ~IN;
 137 endmodule
 138
 139 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 140
 141         parameter PWRDN_EN = 0;
 142         parameter AUTO_PWRDN = 0;
 143         parameter OUT_DIV = 1;
 144
 145         initial CLKOUT = 0;
 146
 147         //auto powerdown not implemented for simulation
 148         //output dividers not implemented for simulation
 149
 150         always begin
 151                 if(PWRDN)
 152                         CLKOUT = 0;
 153                 else begin
 154                         //half period of 1730 Hz
 155                         #289017;
 156                         CLKOUT = ~CLKOUT;
 157                 end
 158         end
 159
 160 endmodule
 161
 162 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
 163
 164         parameter GAIN = 1;
 165         parameter INPUT_MODE = "SINGLE";
 166
 167         initial VOUT = 0;
 168
 169         //cannot simulate mixed signal IP
 170
 171 endmodule
 172
 173 module GP_POR(output reg RST_DONE);
 174         parameter POR_TIME = 500;
 175
 176         initial begin
 177                 RST_DONE = 0;
 178
 179                 if(POR_TIME == 4)
 180                         #4000;
 181                 else if(POR_TIME == 500)
 182                         #500000;
 183                 else begin
 184                         $display("ERROR: bad POR_TIME for GP_POR cell");
 185                         $finish;
 186                 end
 187
 188                 RST_DONE = 1;
 189
 190         end
 191
 192 endmodule
 193
 194 module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 195
 196         parameter PWRDN_EN = 0;
 197         parameter AUTO_PWRDN = 0;
 198         parameter PRE_DIV = 1;
 199         parameter FABRIC_DIV = 1;
 200         parameter OSC_FREQ = "25k";
 201
 202         initial CLKOUT_PREDIV = 0;
 203         initial CLKOUT_FABRIC = 0;
 204
 205         //output dividers not implemented for simulation
 206         //auto powerdown not implemented for simulation
 207
 208         always begin
 209                 if(PWRDN) begin
 210                         CLKOUT_PREDIV = 0;
 211                         CLKOUT_FABRIC = 0;
 212                 end
 213                 else begin
 214
 215                         if(OSC_FREQ == "25k") begin
 216                                 //half period of 25 kHz
 217                                 #20000;
 218                         end
 219
 220                         else begin
 221                                 //half period of 2 MHz
 222                                 #250;
 223                         end
 224
 225                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 226                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 227                 end
 228         end
 229
 230 endmodule
 231
 232 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 233
 234         parameter PWRDN_EN = 0;
 235         parameter AUTO_PWRDN = 0;
 236         parameter PRE_DIV = 1;
 237         parameter FABRIC_DIV = 1;
 238
 239         initial CLKOUT_PREDIV = 0;
 240         initial CLKOUT_FABRIC = 0;
 241
 242         //output dividers not implemented for simulation
 243         //auto powerdown not implemented for simulation
 244
 245         always begin
 246                 if(PWRDN) begin
 247                         CLKOUT_PREDIV = 0;
 248                         CLKOUT_FABRIC = 0;
 249                 end
 250                 else begin
 251                         //half period of 27 MHz
 252                         #18.518;
 253                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 254                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 255                 end
 256         end
 257
 258 endmodule
 259
 260 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 261
 262         parameter OUTA_DELAY = 1;
 263         parameter OUTA_INVERT = 0;
 264         parameter OUTB_DELAY = 1;
 265
 266         reg[15:0] shreg = 0;
 267
 268         always @(posedge clk, negedge nRST) begin
 269
 270                 if(!nRST)
 271                         shreg = 0;
 272
 273                 else
 274                         shreg <= {shreg[14:0], IN};
 275
 276         end
 277
 278         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1];
 279         assign OUTB = shreg[OUTB_DELAY - 1];
 280
 281 endmodule
 282
 283 //keep constraint needed to prevent optimization since we have no outputs
 284 (* keep *)
 285 module GP_SYSRESET(input RST);
 286         parameter RESET_MODE = "RISING";
 287
 288         //cannot simulate whole system reset
 289
 290 endmodule
 291
 292 module GP_VDD(output OUT);
 293        assign OUT = 1;
 294 endmodule
 295
 296 module GP_VREF(input VIN, output reg VOUT);
 297         parameter VIN_DIV = 1;
 298         parameter VREF = 0;
 299         //cannot simulate mixed signal IP
 300 endmodule
 301
 302 module GP_VSS(output OUT);
 303        assign OUT = 0;
 304 endmodule