techlibs/greenpak4/cells_sim.v

   1 `timescale 1ns/1ps
   2
   3 module GP_2LUT(input IN0, IN1, output OUT);
   4         parameter [3:0] INIT = 0;
   5         assign OUT = INIT[{IN1, IN0}];
   6 endmodule
   7
   8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   9         parameter [7:0] INIT = 0;
  10         assign OUT = INIT[{IN2, IN1, IN0}];
  11 endmodule
  12
  13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  14         parameter [15:0] INIT = 0;
  15         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  16 endmodule
  17
  18 module GP_ABUF(input wire IN, output wire OUT);
  19
  20         assign OUT = IN;
  21
  22         //must be 1, 5, 20, 50
  23         //values >1 only available with Vdd > 2.7V
  24         parameter BANDWIDTH_KHZ = 1;
  25
  26         //cannot simulate mixed signal IP
  27
  28 endmodule
  29
  30 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  31
  32         parameter BANDWIDTH = "HIGH";
  33         parameter VIN_ATTEN = 1;
  34         parameter VIN_ISRC_EN = 0;
  35         parameter HYSTERESIS = 0;
  36
  37         initial OUT = 0;
  38
  39         //cannot simulate mixed signal IP
  40
  41 endmodule
  42
  43 module GP_BANDGAP(output reg OK);
  44         parameter AUTO_PWRDN = 1;
  45         parameter CHOPPER_EN = 1;
  46         parameter OUT_DELAY = 100;
  47
  48         //cannot simulate mixed signal IP
  49
  50 endmodule
  51
  52 module GP_CLKBUF(input wire IN, output wire OUT);
  53         assign OUT = IN;
  54 endmodule
  55
  56 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  57
  58         parameter RESET_MODE    = "RISING";
  59
  60         parameter COUNT_TO              = 8'h1;
  61         parameter CLKIN_DIVIDE  = 1;
  62
  63         //more complex hard IP blocks are not supported for simulation yet
  64
  65         reg[7:0] count = COUNT_TO;
  66
  67         //Combinatorially output whenever we wrap low
  68         always @(*) begin
  69                 OUT <= (count == 8'h0);
  70         end
  71
  72         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  73         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  74         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  75         always @(posedge CLK) begin
  76
  77                 count           <= count - 1'd1;
  78
  79                 if(count == 0)
  80                         count   <= COUNT_TO;
  81
  82                 /*
  83                 if((RESET_MODE == "RISING") && RST)
  84                         count   <= 0;
  85                 if((RESET_MODE == "FALLING") && !RST)
  86                         count   <= 0;
  87                 if((RESET_MODE == "BOTH") && RST)
  88                         count   <= 0;
  89                 */
  90         end
  91
  92 endmodule
  93
  94 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  95
  96         parameter RESET_MODE    = "RISING";
  97
  98         parameter COUNT_TO              = 14'h1;
  99         parameter CLKIN_DIVIDE  = 1;
 100
 101         //more complex hard IP blocks are not supported for simulation yet
 102
 103 endmodule
 104
 105 module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 106                      input UP, input KEEP);
 107
 108         parameter RESET_MODE    = "RISING";
 109         parameter RESET_VALUE   = "ZERO";
 110
 111         parameter COUNT_TO              = 8'h1;
 112         parameter CLKIN_DIVIDE  = 1;
 113
 114         //more complex hard IP blocks are not supported for simulation yet
 115
 116 endmodule
 117
 118 module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 119                       input UP, input KEEP);
 120
 121         parameter RESET_MODE    = "RISING";
 122         parameter RESET_VALUE   = "ZERO";
 123
 124         parameter COUNT_TO              = 14'h1;
 125         parameter CLKIN_DIVIDE  = 1;
 126
 127         //more complex hard IP blocks are not supported for simulation yet
 128
 129 endmodule
 130
 131 module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 132
 133         initial VOUT = 0;
 134
 135         //analog hard IP is not supported for simulation
 136
 137 endmodule
 138
 139 module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg OUTP, output reg OUTN);
 140         //TODO finish implementing
 141 endmodule
 142
 143 module GP_DCMPREF(output reg[7:0]OUT);
 144         parameter[7:0] REF_VAL = 8'h00;
 145         initial OUT = REF_VAL;
 146 endmodule
 147
 148 module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
 149
 150         always @(*) begin
 151                 case(SEL)
 152                         2'd00: begin
 153                                 OUTA <= IN0;
 154                                 OUTB <= IN3;
 155                         end
 156
 157                         2'd01: begin
 158                                 OUTA <= IN1;
 159                                 OUTB <= IN2;
 160                         end
 161
 162                         2'd02: begin
 163                                 OUTA <= IN2;
 164                                 OUTB <= IN1;
 165                         end
 166
 167                         2'd03: begin
 168                                 OUTA <= IN3;
 169                                 OUTB <= IN0;
 170                         end
 171
 172                 endcase
 173         end
 174 endmodule
 175
 176 module GP_DELAY(input IN, output reg OUT);
 177
 178         parameter DELAY_STEPS = 1;
 179         parameter GLITCH_FILTER = 0;
 180
 181         initial OUT = 0;
 182
 183         generate
 184
 185                 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
 186                 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
 187                 always @(*) begin
 188                         case(DELAY_STEPS)
 189                                 1: #166 OUT = IN;
 190                                 2: #318 OUT = IN;
 191                                 2: #471 OUT = IN;
 192                                 3: #622 OUT = IN;
 193                                 default: begin
 194                                         $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
 195                                         $finish;
 196                                 end
 197                         endcase
 198                 end
 199
 200         endgenerate
 201
 202 endmodule
 203
 204 module GP_DFF(input D, CLK, output reg Q);
 205         parameter [0:0] INIT = 1'bx;
 206         initial Q = INIT;
 207         always @(posedge CLK) begin
 208                 Q <= D;
 209         end
 210 endmodule
 211
 212 module GP_DFFI(input D, CLK, output reg nQ);
 213         parameter [0:0] INIT = 1'bx;
 214         initial nQ = INIT;
 215         always @(posedge CLK) begin
 216                 nQ <= ~D;
 217         end
 218 endmodule
 219
 220 module GP_DFFR(input D, CLK, nRST, output reg Q);
 221         parameter [0:0] INIT = 1'bx;
 222         initial Q = INIT;
 223         always @(posedge CLK, negedge nRST) begin
 224                 if (!nRST)
 225                         Q <= 1'b0;
 226                 else
 227                         Q <= D;
 228         end
 229 endmodule
 230
 231 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
 232         parameter [0:0] INIT = 1'bx;
 233         initial nQ = INIT;
 234         always @(posedge CLK, negedge nRST) begin
 235                 if (!nRST)
 236                         nQ <= 1'b1;
 237                 else
 238                         nQ <= ~D;
 239         end
 240 endmodule
 241
 242 module GP_DFFS(input D, CLK, nSET, output reg Q);
 243         parameter [0:0] INIT = 1'bx;
 244         initial Q = INIT;
 245         always @(posedge CLK, negedge nSET) begin
 246                 if (!nSET)
 247                         Q <= 1'b1;
 248                 else
 249                         Q <= D;
 250         end
 251 endmodule
 252
 253 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
 254         parameter [0:0] INIT = 1'bx;
 255         initial nQ = INIT;
 256         always @(posedge CLK, negedge nSET) begin
 257                 if (!nSET)
 258                         nQ <= 1'b0;
 259                 else
 260                         nQ <= ~D;
 261         end
 262 endmodule
 263
 264 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 265         parameter [0:0] INIT = 1'bx;
 266         parameter [0:0] SRMODE = 1'bx;
 267         initial Q = INIT;
 268         always @(posedge CLK, negedge nSR) begin
 269                 if (!nSR)
 270                         Q <= SRMODE;
 271                 else
 272                         Q <= D;
 273         end
 274 endmodule
 275
 276 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
 277         parameter [0:0] INIT = 1'bx;
 278         parameter [0:0] SRMODE = 1'bx;
 279         initial nQ = INIT;
 280         always @(posedge CLK, negedge nSR) begin
 281                 if (!nSR)
 282                         nQ <= ~SRMODE;
 283                 else
 284                         nQ <= ~D;
 285         end
 286 endmodule
 287
 288 module GP_DLATCH(input D, input nCLK, output reg Q);
 289         parameter [0:0] INIT = 1'bx;
 290         initial Q = INIT;
 291         always @(*) begin
 292                 if(!nCLK)
 293                         Q <= D;
 294         end
 295 endmodule
 296
 297 module GP_DLATCHI(input D, input nCLK, output reg nQ);
 298         parameter [0:0] INIT = 1'bx;
 299         initial nQ = INIT;
 300         always @(*) begin
 301                 if(!nCLK)
 302                         nQ <= ~D;
 303         end
 304 endmodule
 305
 306 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
 307         parameter [0:0] INIT = 1'bx;
 308         initial Q = INIT;
 309         always @(*) begin
 310                 if(!nRST)
 311                         Q <= 1'b0;
 312                 else if(!nCLK)
 313                         Q <= D;
 314         end
 315 endmodule
 316
 317 module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
 318         parameter [0:0] INIT = 1'bx;
 319         initial nQ = INIT;
 320         always @(*) begin
 321                 if(!nRST)
 322                         nQ <= 1'b1;
 323                 else if(!nCLK)
 324                         nQ <= ~D;
 325         end
 326 endmodule
 327
 328 module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
 329         parameter [0:0] INIT = 1'bx;
 330         initial Q = INIT;
 331         always @(*) begin
 332                 if(!nSET)
 333                         Q <= 1'b1;
 334                 else if(!nCLK)
 335                         Q <= D;
 336         end
 337 endmodule
 338
 339 module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
 340         parameter [0:0] INIT = 1'bx;
 341         initial nQ = INIT;
 342         always @(*) begin
 343                 if(!nSET)
 344                         nQ <= 1'b0;
 345                 else if(!nCLK)
 346                         nQ <= ~D;
 347         end
 348 endmodule
 349
 350 module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
 351         parameter [0:0] INIT = 1'bx;
 352         parameter[0:0] SRMODE = 1'bx;
 353         initial Q = INIT;
 354         always @(*) begin
 355                 if(!nSR)
 356                         Q <= SRMODE;
 357                 else if(!nCLK)
 358                         Q <= D;
 359         end
 360 endmodule
 361
 362 module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
 363         parameter [0:0] INIT = 1'bx;
 364         parameter[0:0] SRMODE = 1'bx;
 365         initial nQ = INIT;
 366         always @(*) begin
 367                 if(!nSR)
 368                         nQ <= ~SRMODE;
 369                 else if(!nCLK)
 370                         nQ <= ~D;
 371         end
 372 endmodule
 373
 374 module GP_EDGEDET(input IN, output reg OUT);
 375
 376         parameter EDGE_DIRECTION = "RISING";
 377         parameter DELAY_STEPS = 1;
 378         parameter GLITCH_FILTER = 0;
 379
 380         //not implemented for simulation
 381
 382 endmodule
 383
 384 module GP_IBUF(input IN, output OUT);
 385         assign OUT = IN;
 386 endmodule
 387
 388 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
 389         assign OUT = IO;
 390         assign IO = OE ? IN : 1'bz;
 391 endmodule
 392
 393 module GP_INV(input IN, output OUT);
 394         assign OUT = ~IN;
 395 endmodule
 396
 397 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 398
 399         parameter PWRDN_EN = 0;
 400         parameter AUTO_PWRDN = 0;
 401         parameter OUT_DIV = 1;
 402
 403         initial CLKOUT = 0;
 404
 405         //auto powerdown not implemented for simulation
 406         //output dividers not implemented for simulation
 407
 408         always begin
 409                 if(PWRDN)
 410                         CLKOUT = 0;
 411                 else begin
 412                         //half period of 1730 Hz
 413                         #289017;
 414                         CLKOUT = ~CLKOUT;
 415                 end
 416         end
 417
 418 endmodule
 419
 420 module GP_OBUF(input IN, output OUT);
 421         assign OUT = IN;
 422 endmodule
 423
 424 module GP_OBUFT(input IN, input OE, output OUT);
 425         assign OUT = OE ? IN : 1'bz;
 426 endmodule
 427
 428 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
 429
 430         parameter GAIN = 1;
 431         parameter INPUT_MODE = "SINGLE";
 432
 433         initial VOUT = 0;
 434
 435         //cannot simulate mixed signal IP
 436
 437 endmodule
 438
 439 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 440         initial OUT = 0;
 441         parameter PATTERN_DATA = 16'h0;
 442         parameter PATTERN_LEN = 5'd16;
 443
 444         reg[3:0] count = 0;
 445         always @(posedge CLK) begin
 446                 if(!nRST)
 447                         OUT <= PATTERN_DATA[0];
 448
 449                 else begin
 450                         count <= count + 1;
 451                         OUT <= PATTERN_DATA[count];
 452
 453                         if( (count + 1) == PATTERN_LEN)
 454                                 count <= 0;
 455                 end
 456         end
 457
 458 endmodule
 459
 460 module GP_PWRDET(output reg VDD_LOW);
 461         initial VDD_LOW = 0;
 462 endmodule
 463
 464 module GP_POR(output reg RST_DONE);
 465         parameter POR_TIME = 500;
 466
 467         initial begin
 468                 RST_DONE = 0;
 469
 470                 if(POR_TIME == 4)
 471                         #4000;
 472                 else if(POR_TIME == 500)
 473                         #500000;
 474                 else begin
 475                         $display("ERROR: bad POR_TIME for GP_POR cell");
 476                         $finish;
 477                 end
 478
 479                 RST_DONE = 1;
 480
 481         end
 482
 483 endmodule
 484
 485 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 486
 487         parameter PWRDN_EN = 0;
 488         parameter AUTO_PWRDN = 0;
 489         parameter HARDIP_DIV = 1;
 490         parameter FABRIC_DIV = 1;
 491         parameter OSC_FREQ = "25k";
 492
 493         initial CLKOUT_HARDIP = 0;
 494         initial CLKOUT_FABRIC = 0;
 495
 496         //output dividers not implemented for simulation
 497         //auto powerdown not implemented for simulation
 498
 499         always begin
 500                 if(PWRDN) begin
 501                         CLKOUT_HARDIP = 0;
 502                         CLKOUT_FABRIC = 0;
 503                 end
 504                 else begin
 505
 506                         if(OSC_FREQ == "25k") begin
 507                                 //half period of 25 kHz
 508                                 #20000;
 509                         end
 510
 511                         else begin
 512                                 //half period of 2 MHz
 513                                 #250;
 514                         end
 515
 516                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 517                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 518                 end
 519         end
 520
 521 endmodule
 522
 523 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 524
 525         parameter PWRDN_EN = 0;
 526         parameter AUTO_PWRDN = 0;
 527         parameter HARDIP_DIV = 1;
 528         parameter FABRIC_DIV = 1;
 529
 530         initial CLKOUT_HARDIP = 0;
 531         initial CLKOUT_FABRIC = 0;
 532
 533         //output dividers not implemented for simulation
 534         //auto powerdown not implemented for simulation
 535
 536         always begin
 537                 if(PWRDN) begin
 538                         CLKOUT_HARDIP = 0;
 539                         CLKOUT_FABRIC = 0;
 540                 end
 541                 else begin
 542                         //half period of 27 MHz
 543                         #18.518;
 544                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 545                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 546                 end
 547         end
 548
 549 endmodule
 550
 551 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 552
 553         parameter OUTA_TAP = 1;
 554         parameter OUTA_INVERT = 0;
 555         parameter OUTB_TAP = 1;
 556
 557         reg[15:0] shreg = 0;
 558
 559         always @(posedge CLK, negedge nRST) begin
 560
 561                 if(!nRST)
 562                         shreg = 0;
 563
 564                 else
 565                         shreg <= {shreg[14:0], IN};
 566
 567         end
 568
 569         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
 570         assign OUTB = shreg[OUTB_TAP - 1];
 571
 572 endmodule
 573
 574 //keep constraint needed to prevent optimization since we have no outputs
 575 (* keep *)
 576 module GP_SYSRESET(input RST);
 577         parameter RESET_MODE = "EDGE";
 578         parameter EDGE_SPEED = 4;
 579
 580         //cannot simulate whole system reset
 581
 582 endmodule
 583
 584 module GP_VDD(output OUT);
 585        assign OUT = 1;
 586 endmodule
 587
 588 module GP_VREF(input VIN, output reg VOUT);
 589         parameter VIN_DIV = 1;
 590         parameter VREF = 0;
 591         //cannot simulate mixed signal IP
 592 endmodule
 593
 594 module GP_VSS(output OUT);
 595        assign OUT = 0;
 596 endmodule