3 module GP_2LUT(input IN0, IN1, output OUT);
4 parameter [3:0] INIT = 0;
5 assign OUT = INIT[{IN1, IN0}];
8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
9 parameter [7:0] INIT = 0;
10 assign OUT = INIT[{IN2, IN1, IN0}];
13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
14 parameter [15:0] INIT = 0;
15 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
18 module GP_ABUF(input wire IN, output wire OUT);
22 //must be 1, 5, 20, 50
23 //values >1 only available with Vdd > 2.7V
24 parameter BANDWIDTH_KHZ = 1;
26 //cannot simulate mixed signal IP
30 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
32 parameter BANDWIDTH = "HIGH";
33 parameter VIN_ATTEN = 1;
34 parameter VIN_ISRC_EN = 0;
35 parameter HYSTERESIS = 0;
39 //cannot simulate mixed signal IP
43 module GP_BANDGAP(output reg OK);
44 parameter AUTO_PWRDN = 1;
45 parameter CHOPPER_EN = 1;
46 parameter OUT_DELAY = 100;
48 //cannot simulate mixed signal IP
52 module GP_CLKBUF(input wire IN, output wire OUT);
56 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
58 parameter RESET_MODE = "RISING";
60 parameter COUNT_TO = 8'h1;
61 parameter CLKIN_DIVIDE = 1;
63 //more complex hard IP blocks are not supported for simulation yet
65 reg[7:0] count = COUNT_TO;
67 //Combinatorially output whenever we wrap low
69 OUT <= (count == 8'h0);
72 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
73 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
74 //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
75 always @(posedge CLK) begin
77 count <= count - 1'd1;
83 if((RESET_MODE == "RISING") && RST)
85 if((RESET_MODE == "FALLING") && !RST)
87 if((RESET_MODE == "BOTH") && RST)
94 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
96 parameter RESET_MODE = "RISING";
98 parameter COUNT_TO = 14'h1;
99 parameter CLKIN_DIVIDE = 1;
101 //more complex hard IP blocks are not supported for simulation yet
105 module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
106 input UP, input KEEP);
108 parameter RESET_MODE = "RISING";
109 parameter RESET_VALUE = "ZERO";
111 parameter COUNT_TO = 8'h1;
112 parameter CLKIN_DIVIDE = 1;
114 //more complex hard IP blocks are not supported for simulation yet
118 module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
119 input UP, input KEEP);
121 parameter RESET_MODE = "RISING";
122 parameter RESET_VALUE = "ZERO";
124 parameter COUNT_TO = 14'h1;
125 parameter CLKIN_DIVIDE = 1;
127 //more complex hard IP blocks are not supported for simulation yet
131 module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
135 //analog hard IP is not supported for simulation
139 module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg OUTP, output reg OUTN);
140 //TODO finish implementing
143 module GP_DCMPREF(output reg[7:0]OUT);
144 parameter[7:0] REF_VAL = 8'h00;
145 initial OUT = REF_VAL;
148 module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
176 module GP_DELAY(input IN, output reg OUT);
178 parameter DELAY_STEPS = 1;
179 parameter GLITCH_FILTER = 0;
185 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
186 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
194 $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
204 module GP_DFF(input D, CLK, output reg Q);
205 parameter [0:0] INIT = 1'bx;
207 always @(posedge CLK) begin
212 module GP_DFFI(input D, CLK, output reg nQ);
213 parameter [0:0] INIT = 1'bx;
215 always @(posedge CLK) begin
220 module GP_DFFR(input D, CLK, nRST, output reg Q);
221 parameter [0:0] INIT = 1'bx;
223 always @(posedge CLK, negedge nRST) begin
231 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
232 parameter [0:0] INIT = 1'bx;
234 always @(posedge CLK, negedge nRST) begin
242 module GP_DFFS(input D, CLK, nSET, output reg Q);
243 parameter [0:0] INIT = 1'bx;
245 always @(posedge CLK, negedge nSET) begin
253 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
254 parameter [0:0] INIT = 1'bx;
256 always @(posedge CLK, negedge nSET) begin
264 module GP_DFFSR(input D, CLK, nSR, output reg Q);
265 parameter [0:0] INIT = 1'bx;
266 parameter [0:0] SRMODE = 1'bx;
268 always @(posedge CLK, negedge nSR) begin
276 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
277 parameter [0:0] INIT = 1'bx;
278 parameter [0:0] SRMODE = 1'bx;
280 always @(posedge CLK, negedge nSR) begin
288 module GP_DLATCH(input D, input nCLK, output reg Q);
289 parameter [0:0] INIT = 1'bx;
297 module GP_DLATCHI(input D, input nCLK, output reg nQ);
298 parameter [0:0] INIT = 1'bx;
306 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
307 parameter [0:0] INIT = 1'bx;
317 module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
318 parameter [0:0] INIT = 1'bx;
328 module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
329 parameter [0:0] INIT = 1'bx;
339 module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
340 parameter [0:0] INIT = 1'bx;
350 module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
351 parameter [0:0] INIT = 1'bx;
352 parameter[0:0] SRMODE = 1'bx;
362 module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
363 parameter [0:0] INIT = 1'bx;
364 parameter[0:0] SRMODE = 1'bx;
374 module GP_EDGEDET(input IN, output reg OUT);
376 parameter EDGE_DIRECTION = "RISING";
377 parameter DELAY_STEPS = 1;
378 parameter GLITCH_FILTER = 0;
380 //not implemented for simulation
384 module GP_IBUF(input IN, output OUT);
388 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
390 assign IO = OE ? IN : 1'bz;
393 module GP_INV(input IN, output OUT);
397 module GP_LFOSC(input PWRDN, output reg CLKOUT);
399 parameter PWRDN_EN = 0;
400 parameter AUTO_PWRDN = 0;
401 parameter OUT_DIV = 1;
405 //auto powerdown not implemented for simulation
406 //output dividers not implemented for simulation
412 //half period of 1730 Hz
420 module GP_OBUF(input IN, output OUT);
424 module GP_OBUFT(input IN, input OE, output OUT);
425 assign OUT = OE ? IN : 1'bz;
428 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
431 parameter INPUT_MODE = "SINGLE";
435 //cannot simulate mixed signal IP
439 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
441 parameter PATTERN_DATA = 16'h0;
442 parameter PATTERN_LEN = 5'd16;
445 always @(posedge CLK) begin
447 OUT <= PATTERN_DATA[0];
451 OUT <= PATTERN_DATA[count];
453 if( (count + 1) == PATTERN_LEN)
460 module GP_PWRDET(output reg VDD_LOW);
464 module GP_POR(output reg RST_DONE);
465 parameter POR_TIME = 500;
472 else if(POR_TIME == 500)
475 $display("ERROR: bad POR_TIME for GP_POR cell");
485 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
487 parameter PWRDN_EN = 0;
488 parameter AUTO_PWRDN = 0;
489 parameter HARDIP_DIV = 1;
490 parameter FABRIC_DIV = 1;
491 parameter OSC_FREQ = "25k";
493 initial CLKOUT_HARDIP = 0;
494 initial CLKOUT_FABRIC = 0;
496 //output dividers not implemented for simulation
497 //auto powerdown not implemented for simulation
506 if(OSC_FREQ == "25k") begin
507 //half period of 25 kHz
512 //half period of 2 MHz
516 CLKOUT_HARDIP = ~CLKOUT_HARDIP;
517 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
523 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
525 parameter PWRDN_EN = 0;
526 parameter AUTO_PWRDN = 0;
527 parameter HARDIP_DIV = 1;
528 parameter FABRIC_DIV = 1;
530 initial CLKOUT_HARDIP = 0;
531 initial CLKOUT_FABRIC = 0;
533 //output dividers not implemented for simulation
534 //auto powerdown not implemented for simulation
542 //half period of 27 MHz
544 CLKOUT_HARDIP = ~CLKOUT_HARDIP;
545 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
551 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
553 parameter OUTA_TAP = 1;
554 parameter OUTA_INVERT = 0;
555 parameter OUTB_TAP = 1;
559 always @(posedge CLK, negedge nRST) begin
565 shreg <= {shreg[14:0], IN};
569 assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
570 assign OUTB = shreg[OUTB_TAP - 1];
574 //keep constraint needed to prevent optimization since we have no outputs
576 module GP_SYSRESET(input RST);
577 parameter RESET_MODE = "EDGE";
578 parameter EDGE_SPEED = 4;
580 //cannot simulate whole system reset
584 module GP_VDD(output OUT);
588 module GP_VREF(input VIN, output reg VOUT);
589 parameter VIN_DIV = 1;
591 //cannot simulate mixed signal IP
594 module GP_VSS(output OUT);