techlibs/greenpak4/cells_sim.v

   1 module GP_2LUT(input IN0, IN1, output OUT);
   2         parameter [3:0] INIT = 0;
   3         assign OUT = INIT[{IN1, IN0}];
   4 endmodule
   5
   6 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   7         parameter [7:0] INIT = 0;
   8         assign OUT = INIT[{IN2, IN1, IN0}];
   9 endmodule
  10
  11 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  12         parameter [15:0] INIT = 0;
  13         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  14 endmodule
  15
  16 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  17
  18         parameter BANDWIDTH = "HIGH";
  19         parameter VIN_ATTEN = 1;
  20         parameter VIN_ISRC_EN = 0;
  21         parameter HYSTERESIS = 0;
  22
  23         initial OUT = 0;
  24
  25         //cannot simulate mixed signal IP
  26
  27 endmodule
  28
  29 module GP_BANDGAP(output reg OK, output reg VOUT);
  30         parameter AUTO_PWRDN = 1;
  31         parameter CHOPPER_EN = 1;
  32         parameter OUT_DELAY = 100;
  33
  34         //cannot simulate mixed signal IP
  35
  36 endmodule
  37
  38 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  39
  40         parameter RESET_MODE    = "RISING";
  41
  42         parameter COUNT_TO              = 8'h1;
  43         parameter CLKIN_DIVIDE  = 1;
  44
  45         //more complex hard IP blocks are not supported for simulation yet
  46
  47         reg[7:0] count = COUNT_TO;
  48
  49         //Combinatorially output whenever we wrap low
  50         always @(*) begin
  51                 OUT <= (count == 8'h0);
  52         end
  53
  54         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  55         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  56         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  57         always @(posedge CLK) begin
  58
  59                 count           <= count - 1'd1;
  60
  61                 if(count == 0)
  62                         count   <= COUNT_MAX;
  63
  64                 /*
  65                 if((RESET_MODE == "RISING") && RST)
  66                         count   <= 0;
  67                 if((RESET_MODE == "FALLING") && !RST)
  68                         count   <= 0;
  69                 if((RESET_MODE == "BOTH") && RST)
  70                         count   <= 0;
  71                 */
  72         end
  73
  74 endmodule
  75
  76 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  77
  78         parameter RESET_MODE    = "RISING";
  79
  80         parameter COUNT_TO              = 14'h1;
  81         parameter CLKIN_DIVIDE  = 1;
  82
  83         //more complex hard IP blocks are not supported for simulation yet
  84
  85 endmodule
  86
  87 module GP_DFF(input D, CLK, output reg Q);
  88         parameter [0:0] INIT = 1'bx;
  89         initial Q = INIT;
  90         always @(posedge CLK) begin
  91                 Q <= D;
  92         end
  93 endmodule
  94
  95 module GP_DFFR(input D, CLK, nRST, output reg Q);
  96         parameter [0:0] INIT = 1'bx;
  97         initial Q = INIT;
  98         always @(posedge CLK, negedge nRST) begin
  99                 if (!nRST)
 100                         Q <= 1'b0;
 101                 else
 102                         Q <= D;
 103         end
 104 endmodule
 105
 106 module GP_DFFS(input D, CLK, nSET, output reg Q);
 107         parameter [0:0] INIT = 1'bx;
 108         initial Q = INIT;
 109         always @(posedge CLK, negedge nSET) begin
 110                 if (!nSET)
 111                         Q <= 1'b1;
 112                 else
 113                         Q <= D;
 114         end
 115 endmodule
 116
 117 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 118         parameter [0:0] INIT = 1'bx;
 119         parameter [0:0] SRMODE = 1'bx;
 120         initial Q = INIT;
 121         always @(posedge CLK, negedge nSR) begin
 122                 if (!nSR)
 123                         Q <= SRMODE;
 124                 else
 125                         Q <= D;
 126         end
 127 endmodule
 128
 129 module GP_INV(input IN, output OUT);
 130         assign OUT = ~IN;
 131 endmodule
 132
 133 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 134
 135         parameter PWRDN_EN = 0;
 136         parameter AUTO_PWRDN = 0;
 137         parameter OUT_DIV = 1;
 138
 139         initial CLKOUT = 0;
 140
 141         //auto powerdown not implemented for simulation
 142         //output dividers not implemented for simulation
 143
 144         always begin
 145                 if(PWRDN)
 146                         CLKOUT = 0;
 147                 else begin
 148                         //half period of 1730 Hz
 149                         #289017;
 150                         CLKOUT = ~CLKOUT;
 151                 end
 152         end
 153
 154 endmodule
 155
 156 module GP_POR(output reg RST_DONE);
 157         parameter POR_TIME = 500;
 158
 159         initial begin
 160                 RST_DONE = 0;
 161
 162                 if(POR_TIME == 4)
 163                         #4000;
 164                 else if(POR_TIME == 500)
 165                         #500000;
 166                 else begin
 167                         $display("ERROR: bad POR_TIME for GP_POR cell");
 168                         $finish;
 169                 end
 170
 171                 RST_DONE = 1;
 172
 173         end
 174
 175 endmodule
 176
 177 module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 178
 179         parameter PWRDN_EN = 0;
 180         parameter AUTO_PWRDN = 0;
 181         parameter PRE_DIV = 1;
 182         parameter FABRIC_DIV = 1;
 183         parameter OSC_FREQ = "25k";
 184
 185         initial CLKOUT_PREDIV = 0;
 186         initial CLKOUT_FABRIC = 0;
 187
 188         //output dividers not implemented for simulation
 189         //auto powerdown not implemented for simulation
 190
 191         always begin
 192                 if(PWRDN) begin
 193                         CLKOUT_PREDIV = 0;
 194                         CLKOUT_FABRIC = 0;
 195                 end
 196                 else begin
 197
 198                         if(OSC_FREQ == "25k") begin
 199                                 //half period of 25 kHz
 200                                 #20000;
 201                         end
 202
 203                         else begin
 204                                 //half period of 2 MHz
 205                                 #250;
 206                         end
 207
 208                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 209                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 210                 end
 211         end
 212
 213 endmodule
 214
 215 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 216
 217         parameter PWRDN_EN = 0;
 218         parameter AUTO_PWRDN = 0;
 219         parameter PRE_DIV = 1;
 220         parameter FABRIC_DIV = 1;
 221
 222         initial CLKOUT_PREDIV = 0;
 223         initial CLKOUT_FABRIC = 0;
 224
 225         //output dividers not implemented for simulation
 226         //auto powerdown not implemented for simulation
 227
 228         always begin
 229                 if(PWRDN) begin
 230                         CLKOUT_PREDIV = 0;
 231                         CLKOUT_FABRIC = 0;
 232                 end
 233                 else begin
 234                         //half period of 27 MHz
 235                         #18.518;
 236                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 237                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 238                 end
 239         end
 240
 241 endmodule
 242
 243 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 244
 245         parameter OUTA_DELAY = 1;
 246         parameter OUTA_INVERT = 0;
 247         parameter OUTB_DELAY = 1;
 248
 249         reg[15:0] shreg = 0;
 250
 251         always @(posedge clk, negedge nRST) begin
 252
 253                 if(!nRST)
 254                         shreg = 0;
 255
 256                 else
 257                         shreg <= {shreg[14:0], IN};
 258
 259         end
 260
 261         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1];
 262         assign OUTB = shreg[OUTB_DELAY - 1];
 263
 264 endmodule
 265
 266 //keep constraint needed to prevent optimization since we have no outputs
 267 (* keep *)
 268 module GP_SYSRESET(input RST);
 269         parameter RESET_MODE = "RISING";
 270
 271         //cannot simulate whole system reset
 272
 273 endmodule
 274
 275 module GP_VDD(output OUT);
 276        assign OUT = 1;
 277 endmodule
 278
 279 module GP_VREF(input VIN, output reg VOUT);
 280         parameter VIN_DIV = 1;
 281         parameter VREF = 0;
 282         //cannot simulate mixed signal IP
 283 endmodule
 284
 285 module GP_VSS(output OUT);
 286        assign OUT = 0;
 287 endmodule