3 module GP_2LUT(input IN0, IN1, output OUT);
4 parameter [3:0] INIT = 0;
5 assign OUT = INIT[{IN1, IN0}];
8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
9 parameter [7:0] INIT = 0;
10 assign OUT = INIT[{IN2, IN1, IN0}];
13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
14 parameter [15:0] INIT = 0;
15 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
18 module GP_ABUF(input wire IN, output wire OUT);
22 //must be 1, 5, 20, 50
23 //values >1 only available with Vdd > 2.7V
24 parameter BANDWIDTH_KHZ = 1;
26 //cannot simulate mixed signal IP
30 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
32 parameter BANDWIDTH = "HIGH";
33 parameter VIN_ATTEN = 1;
34 parameter VIN_ISRC_EN = 0;
35 parameter HYSTERESIS = 0;
39 //cannot simulate mixed signal IP
43 module GP_BANDGAP(output reg OK);
44 parameter AUTO_PWRDN = 1;
45 parameter CHOPPER_EN = 1;
46 parameter OUT_DELAY = 100;
48 //cannot simulate mixed signal IP
52 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
54 parameter RESET_MODE = "RISING";
56 parameter COUNT_TO = 8'h1;
57 parameter CLKIN_DIVIDE = 1;
59 //more complex hard IP blocks are not supported for simulation yet
61 reg[7:0] count = COUNT_TO;
63 //Combinatorially output whenever we wrap low
65 OUT <= (count == 8'h0);
68 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
69 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
70 //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
71 always @(posedge CLK) begin
73 count <= count - 1'd1;
79 if((RESET_MODE == "RISING") && RST)
81 if((RESET_MODE == "FALLING") && !RST)
83 if((RESET_MODE == "BOTH") && RST)
90 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
92 parameter RESET_MODE = "RISING";
94 parameter COUNT_TO = 14'h1;
95 parameter CLKIN_DIVIDE = 1;
97 //more complex hard IP blocks are not supported for simulation yet
101 module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
102 input UP, input KEEP);
104 parameter RESET_MODE = "RISING";
105 parameter RESET_VALUE = "ZERO";
107 parameter COUNT_TO = 8'h1;
108 parameter CLKIN_DIVIDE = 1;
110 //more complex hard IP blocks are not supported for simulation yet
114 module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
115 input UP, input KEEP);
117 parameter RESET_MODE = "RISING";
118 parameter RESET_VALUE = "ZERO";
120 parameter COUNT_TO = 14'h1;
121 parameter CLKIN_DIVIDE = 1;
123 //more complex hard IP blocks are not supported for simulation yet
127 module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
131 //analog hard IP is not supported for simulation
135 module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN);
138 module GP_DCMPREF(output reg[7:0]OUT);
139 parameter[7:0] REF_VAL = 8'h00;
140 initial OUT = REF_VAL;
143 module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
171 module GP_DELAY(input IN, output reg OUT);
173 parameter DELAY_STEPS = 1;
174 parameter GLITCH_FILTER = 0;
180 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
181 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
189 $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
199 module GP_DFF(input D, CLK, output reg Q);
200 parameter [0:0] INIT = 1'bx;
202 always @(posedge CLK) begin
207 module GP_DFFI(input D, CLK, output reg nQ);
208 parameter [0:0] INIT = 1'bx;
210 always @(posedge CLK) begin
215 module GP_DFFR(input D, CLK, nRST, output reg Q);
216 parameter [0:0] INIT = 1'bx;
218 always @(posedge CLK, negedge nRST) begin
226 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
227 parameter [0:0] INIT = 1'bx;
229 always @(posedge CLK, negedge nRST) begin
237 module GP_DFFS(input D, CLK, nSET, output reg Q);
238 parameter [0:0] INIT = 1'bx;
240 always @(posedge CLK, negedge nSET) begin
248 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
249 parameter [0:0] INIT = 1'bx;
251 always @(posedge CLK, negedge nSET) begin
259 module GP_DFFSR(input D, CLK, nSR, output reg Q);
260 parameter [0:0] INIT = 1'bx;
261 parameter [0:0] SRMODE = 1'bx;
263 always @(posedge CLK, negedge nSR) begin
271 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
272 parameter [0:0] INIT = 1'bx;
273 parameter [0:0] SRMODE = 1'bx;
275 always @(posedge CLK, negedge nSR) begin
283 module GP_DLATCH(input D, input nCLK, output reg Q);
284 parameter [0:0] INIT = 1'bx;
292 module GP_DLATCHI(input D, input nCLK, output reg nQ);
293 parameter [0:0] INIT = 1'bx;
301 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
302 parameter [0:0] INIT = 1'bx;
312 module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
313 parameter [0:0] INIT = 1'bx;
323 module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
324 parameter [0:0] INIT = 1'bx;
334 module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
335 parameter [0:0] INIT = 1'bx;
345 module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
346 parameter [0:0] INIT = 1'bx;
347 parameter[0:0] SRMODE = 1'bx;
357 module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
358 parameter [0:0] INIT = 1'bx;
359 parameter[0:0] SRMODE = 1'bx;
369 module GP_EDGEDET(input IN, output reg OUT);
371 parameter EDGE_DIRECTION = "RISING";
372 parameter DELAY_STEPS = 1;
373 parameter GLITCH_FILTER = 0;
375 //not implemented for simulation
379 module GP_IBUF(input IN, output OUT);
383 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
385 assign IO = OE ? IN : 1'bz;
388 module GP_INV(input IN, output OUT);
392 module GP_LFOSC(input PWRDN, output reg CLKOUT);
394 parameter PWRDN_EN = 0;
395 parameter AUTO_PWRDN = 0;
396 parameter OUT_DIV = 1;
400 //auto powerdown not implemented for simulation
401 //output dividers not implemented for simulation
407 //half period of 1730 Hz
415 module GP_OBUF(input IN, output OUT);
419 module GP_OBUFT(input IN, input OE, output OUT);
420 assign OUT = OE ? IN : 1'bz;
423 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
426 parameter INPUT_MODE = "SINGLE";
430 //cannot simulate mixed signal IP
434 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
436 parameter PATTERN_DATA = 16'h0;
437 parameter PATTERN_LEN = 5'd16;
440 always @(posedge CLK) begin
442 OUT <= PATTERN_DATA[0];
446 OUT <= PATTERN_DATA[count];
448 if( (count + 1) == PATTERN_LEN)
455 module GP_PWRDET(output reg VDD_LOW);
459 module GP_POR(output reg RST_DONE);
460 parameter POR_TIME = 500;
467 else if(POR_TIME == 500)
470 $display("ERROR: bad POR_TIME for GP_POR cell");
480 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
482 parameter PWRDN_EN = 0;
483 parameter AUTO_PWRDN = 0;
484 parameter HARDIP_DIV = 1;
485 parameter FABRIC_DIV = 1;
486 parameter OSC_FREQ = "25k";
488 initial CLKOUT_HARDIP = 0;
489 initial CLKOUT_FABRIC = 0;
491 //output dividers not implemented for simulation
492 //auto powerdown not implemented for simulation
501 if(OSC_FREQ == "25k") begin
502 //half period of 25 kHz
507 //half period of 2 MHz
511 CLKOUT_HARDIP = ~CLKOUT_HARDIP;
512 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
518 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
520 parameter PWRDN_EN = 0;
521 parameter AUTO_PWRDN = 0;
522 parameter HARDIP_DIV = 1;
523 parameter FABRIC_DIV = 1;
525 initial CLKOUT_HARDIP = 0;
526 initial CLKOUT_FABRIC = 0;
528 //output dividers not implemented for simulation
529 //auto powerdown not implemented for simulation
537 //half period of 27 MHz
539 CLKOUT_HARDIP = ~CLKOUT_HARDIP;
540 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
546 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
548 parameter OUTA_TAP = 1;
549 parameter OUTA_INVERT = 0;
550 parameter OUTB_TAP = 1;
554 always @(posedge CLK, negedge nRST) begin
560 shreg <= {shreg[14:0], IN};
564 assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
565 assign OUTB = shreg[OUTB_TAP - 1];
569 //keep constraint needed to prevent optimization since we have no outputs
571 module GP_SYSRESET(input RST);
572 parameter RESET_MODE = "EDGE";
573 parameter EDGE_SPEED = 4;
575 //cannot simulate whole system reset
579 module GP_VDD(output OUT);
583 module GP_VREF(input VIN, output reg VOUT);
584 parameter VIN_DIV = 1;
586 //cannot simulate mixed signal IP
589 module GP_VSS(output OUT);