techlibs/greenpak4/cells_sim.v

   1 `timescale 1ns/1ps
   2
   3 module GP_2LUT(input IN0, IN1, output OUT);
   4         parameter [3:0] INIT = 0;
   5         assign OUT = INIT[{IN1, IN0}];
   6 endmodule
   7
   8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   9         parameter [7:0] INIT = 0;
  10         assign OUT = INIT[{IN2, IN1, IN0}];
  11 endmodule
  12
  13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  14         parameter [15:0] INIT = 0;
  15         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  16 endmodule
  17
  18 module GP_ABUF(input wire IN, output wire OUT);
  19
  20         assign OUT = IN;
  21
  22         //must be 1, 5, 20, 50
  23         //values >1 only available with Vdd > 2.7V
  24         parameter BANDWIDTH_KHZ = 1;
  25
  26         //cannot simulate mixed signal IP
  27
  28 endmodule
  29
  30 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  31
  32         parameter BANDWIDTH = "HIGH";
  33         parameter VIN_ATTEN = 1;
  34         parameter VIN_ISRC_EN = 0;
  35         parameter HYSTERESIS = 0;
  36
  37         initial OUT = 0;
  38
  39         //cannot simulate mixed signal IP
  40
  41 endmodule
  42
  43 module GP_BANDGAP(output reg OK);
  44         parameter AUTO_PWRDN = 1;
  45         parameter CHOPPER_EN = 1;
  46         parameter OUT_DELAY = 100;
  47
  48         //cannot simulate mixed signal IP
  49
  50 endmodule
  51
  52 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  53
  54         parameter RESET_MODE    = "RISING";
  55
  56         parameter COUNT_TO              = 8'h1;
  57         parameter CLKIN_DIVIDE  = 1;
  58
  59         //more complex hard IP blocks are not supported for simulation yet
  60
  61         reg[7:0] count = COUNT_TO;
  62
  63         //Combinatorially output whenever we wrap low
  64         always @(*) begin
  65                 OUT <= (count == 8'h0);
  66         end
  67
  68         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  69         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  70         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  71         always @(posedge CLK) begin
  72
  73                 count           <= count - 1'd1;
  74
  75                 if(count == 0)
  76                         count   <= COUNT_TO;
  77
  78                 /*
  79                 if((RESET_MODE == "RISING") && RST)
  80                         count   <= 0;
  81                 if((RESET_MODE == "FALLING") && !RST)
  82                         count   <= 0;
  83                 if((RESET_MODE == "BOTH") && RST)
  84                         count   <= 0;
  85                 */
  86         end
  87
  88 endmodule
  89
  90 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  91
  92         parameter RESET_MODE    = "RISING";
  93
  94         parameter COUNT_TO              = 14'h1;
  95         parameter CLKIN_DIVIDE  = 1;
  96
  97         //more complex hard IP blocks are not supported for simulation yet
  98
  99 endmodule
 100
 101 module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 102                      input UP, input KEEP);
 103
 104         parameter RESET_MODE    = "RISING";
 105         parameter RESET_VALUE   = "ZERO";
 106
 107         parameter COUNT_TO              = 8'h1;
 108         parameter CLKIN_DIVIDE  = 1;
 109
 110         //more complex hard IP blocks are not supported for simulation yet
 111
 112 endmodule
 113
 114 module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 115                       input UP, input KEEP);
 116
 117         parameter RESET_MODE    = "RISING";
 118         parameter RESET_VALUE   = "ZERO";
 119
 120         parameter COUNT_TO              = 14'h1;
 121         parameter CLKIN_DIVIDE  = 1;
 122
 123         //more complex hard IP blocks are not supported for simulation yet
 124
 125 endmodule
 126
 127 module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 128
 129         initial VOUT = 0;
 130
 131         //analog hard IP is not supported for simulation
 132
 133 endmodule
 134
 135 module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN);
 136 endmodule
 137
 138 module GP_DCMPREF(output reg[7:0]OUT);
 139         parameter[7:0] REF_VAL = 8'h00;
 140         initial OUT = REF_VAL;
 141 endmodule
 142
 143 module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
 144
 145         always @(*) begin
 146                 case(SEL)
 147                         2'b00: begin
 148                                 OUTA <= IN0;
 149                                 OUTB <= IN3;
 150                         end
 151
 152                         2'b01: begin
 153                                 OUTA <= IN1;
 154                                 OUTB <= IN2;
 155                         end
 156
 157                         2'b02: begin
 158                                 OUTA <= IN2;
 159                                 OUTB <= IN1;
 160                         end
 161
 162                         2'b03: begin
 163                                 OUTA <= IN3;
 164                                 OUTB <= IN0;
 165                         end
 166
 167                 endcase
 168         end
 169 endmodule
 170
 171 module GP_DELAY(input IN, output reg OUT);
 172
 173         parameter DELAY_STEPS = 1;
 174         parameter GLITCH_FILTER = 0;
 175
 176         initial OUT = 0;
 177
 178         generate
 179
 180                 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
 181                 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
 182                 always @(*) begin
 183                         case(DELAY_STEPS)
 184                                 1: #166 OUT = IN;
 185                                 2: #318 OUT = IN;
 186                                 2: #471 OUT = IN;
 187                                 3: #622 OUT = IN;
 188                                 default: begin
 189                                         $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
 190                                         $finish;
 191                                 end
 192                         endcase
 193                 end
 194
 195         endgenerate
 196
 197 endmodule
 198
 199 module GP_DFF(input D, CLK, output reg Q);
 200         parameter [0:0] INIT = 1'bx;
 201         initial Q = INIT;
 202         always @(posedge CLK) begin
 203                 Q <= D;
 204         end
 205 endmodule
 206
 207 module GP_DFFI(input D, CLK, output reg nQ);
 208         parameter [0:0] INIT = 1'bx;
 209         initial nQ = INIT;
 210         always @(posedge CLK) begin
 211                 nQ <= ~D;
 212         end
 213 endmodule
 214
 215 module GP_DFFR(input D, CLK, nRST, output reg Q);
 216         parameter [0:0] INIT = 1'bx;
 217         initial Q = INIT;
 218         always @(posedge CLK, negedge nRST) begin
 219                 if (!nRST)
 220                         Q <= 1'b0;
 221                 else
 222                         Q <= D;
 223         end
 224 endmodule
 225
 226 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
 227         parameter [0:0] INIT = 1'bx;
 228         initial nQ = INIT;
 229         always @(posedge CLK, negedge nRST) begin
 230                 if (!nRST)
 231                         nQ <= 1'b1;
 232                 else
 233                         nQ <= ~D;
 234         end
 235 endmodule
 236
 237 module GP_DFFS(input D, CLK, nSET, output reg Q);
 238         parameter [0:0] INIT = 1'bx;
 239         initial Q = INIT;
 240         always @(posedge CLK, negedge nSET) begin
 241                 if (!nSET)
 242                         Q <= 1'b1;
 243                 else
 244                         Q <= D;
 245         end
 246 endmodule
 247
 248 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
 249         parameter [0:0] INIT = 1'bx;
 250         initial nQ = INIT;
 251         always @(posedge CLK, negedge nSET) begin
 252                 if (!nSET)
 253                         nQ <= 1'b0;
 254                 else
 255                         nQ <= ~D;
 256         end
 257 endmodule
 258
 259 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 260         parameter [0:0] INIT = 1'bx;
 261         parameter [0:0] SRMODE = 1'bx;
 262         initial Q = INIT;
 263         always @(posedge CLK, negedge nSR) begin
 264                 if (!nSR)
 265                         Q <= SRMODE;
 266                 else
 267                         Q <= D;
 268         end
 269 endmodule
 270
 271 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
 272         parameter [0:0] INIT = 1'bx;
 273         parameter [0:0] SRMODE = 1'bx;
 274         initial nQ = INIT;
 275         always @(posedge CLK, negedge nSR) begin
 276                 if (!nSR)
 277                         nQ <= ~SRMODE;
 278                 else
 279                         nQ <= ~D;
 280         end
 281 endmodule
 282
 283 module GP_DLATCH(input D, input nCLK, output reg Q);
 284         parameter [0:0] INIT = 1'bx;
 285         initial Q = INIT;
 286         always @(*) begin
 287                 if(!nCLK)
 288                         Q <= D;
 289         end
 290 endmodule
 291
 292 module GP_DLATCHI(input D, input nCLK, output reg nQ);
 293         parameter [0:0] INIT = 1'bx;
 294         initial nQ = INIT;
 295         always @(*) begin
 296                 if(!nCLK)
 297                         nQ <= ~D;
 298         end
 299 endmodule
 300
 301 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
 302         parameter [0:0] INIT = 1'bx;
 303         initial Q = INIT;
 304         always @(*) begin
 305                 if(!nRST)
 306                         Q <= 1'b0;
 307                 else if(!nCLK)
 308                         Q <= D;
 309         end
 310 endmodule
 311
 312 module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
 313         parameter [0:0] INIT = 1'bx;
 314         initial nQ = INIT;
 315         always @(*) begin
 316                 if(!nRST)
 317                         nQ <= 1'b1;
 318                 else if(!nCLK)
 319                         nQ <= ~D;
 320         end
 321 endmodule
 322
 323 module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
 324         parameter [0:0] INIT = 1'bx;
 325         initial Q = INIT;
 326         always @(*) begin
 327                 if(!nSET)
 328                         Q <= 1'b1;
 329                 else if(!nCLK)
 330                         Q <= D;
 331         end
 332 endmodule
 333
 334 module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
 335         parameter [0:0] INIT = 1'bx;
 336         initial nQ = INIT;
 337         always @(*) begin
 338                 if(!nSET)
 339                         nQ <= 1'b0;
 340                 else if(!nCLK)
 341                         nQ <= ~D;
 342         end
 343 endmodule
 344
 345 module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
 346         parameter [0:0] INIT = 1'bx;
 347         parameter[0:0] SRMODE = 1'bx;
 348         initial Q = INIT;
 349         always @(*) begin
 350                 if(!nSR)
 351                         Q <= SRMODE;
 352                 else if(!nCLK)
 353                         Q <= D;
 354         end
 355 endmodule
 356
 357 module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
 358         parameter [0:0] INIT = 1'bx;
 359         parameter[0:0] SRMODE = 1'bx;
 360         initial nQ = INIT;
 361         always @(*) begin
 362                 if(!nSR)
 363                         nQ <= ~SRMODE;
 364                 else if(!nCLK)
 365                         nQ <= ~D;
 366         end
 367 endmodule
 368
 369 module GP_EDGEDET(input IN, output reg OUT);
 370
 371         parameter EDGE_DIRECTION = "RISING";
 372         parameter DELAY_STEPS = 1;
 373         parameter GLITCH_FILTER = 0;
 374
 375         //not implemented for simulation
 376
 377 endmodule
 378
 379 module GP_IBUF(input IN, output OUT);
 380         assign OUT = IN;
 381 endmodule
 382
 383 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
 384         assign OUT = IO;
 385         assign IO = OE ? IN : 1'bz;
 386 endmodule
 387
 388 module GP_INV(input IN, output OUT);
 389         assign OUT = ~IN;
 390 endmodule
 391
 392 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 393
 394         parameter PWRDN_EN = 0;
 395         parameter AUTO_PWRDN = 0;
 396         parameter OUT_DIV = 1;
 397
 398         initial CLKOUT = 0;
 399
 400         //auto powerdown not implemented for simulation
 401         //output dividers not implemented for simulation
 402
 403         always begin
 404                 if(PWRDN)
 405                         CLKOUT = 0;
 406                 else begin
 407                         //half period of 1730 Hz
 408                         #289017;
 409                         CLKOUT = ~CLKOUT;
 410                 end
 411         end
 412
 413 endmodule
 414
 415 module GP_OBUF(input IN, output OUT);
 416         assign OUT = IN;
 417 endmodule
 418
 419 module GP_OBUFT(input IN, input OE, output OUT);
 420         assign OUT = OE ? IN : 1'bz;
 421 endmodule
 422
 423 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
 424
 425         parameter GAIN = 1;
 426         parameter INPUT_MODE = "SINGLE";
 427
 428         initial VOUT = 0;
 429
 430         //cannot simulate mixed signal IP
 431
 432 endmodule
 433
 434 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 435         initial OUT = 0;
 436         parameter PATTERN_DATA = 16'h0;
 437         parameter PATTERN_LEN = 5'd16;
 438
 439         reg[3:0] count = 0;
 440         always @(posedge CLK) begin
 441                 if(!nRST)
 442                         OUT <= PATTERN_DATA[0];
 443
 444                 else begin
 445                         count <= count + 1;
 446                         OUT <= PATTERN_DATA[count];
 447
 448                         if( (count + 1) == PATTERN_LEN)
 449                                 count <= 0;
 450                 end
 451         end
 452
 453 endmodule
 454
 455 module GP_PWRDET(output reg VDD_LOW);
 456         initial VDD_LOW = 0;
 457 endmodule
 458
 459 module GP_POR(output reg RST_DONE);
 460         parameter POR_TIME = 500;
 461
 462         initial begin
 463                 RST_DONE = 0;
 464
 465                 if(POR_TIME == 4)
 466                         #4000;
 467                 else if(POR_TIME == 500)
 468                         #500000;
 469                 else begin
 470                         $display("ERROR: bad POR_TIME for GP_POR cell");
 471                         $finish;
 472                 end
 473
 474                 RST_DONE = 1;
 475
 476         end
 477
 478 endmodule
 479
 480 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 481
 482         parameter PWRDN_EN = 0;
 483         parameter AUTO_PWRDN = 0;
 484         parameter HARDIP_DIV = 1;
 485         parameter FABRIC_DIV = 1;
 486         parameter OSC_FREQ = "25k";
 487
 488         initial CLKOUT_HARDIP = 0;
 489         initial CLKOUT_FABRIC = 0;
 490
 491         //output dividers not implemented for simulation
 492         //auto powerdown not implemented for simulation
 493
 494         always begin
 495                 if(PWRDN) begin
 496                         CLKOUT_HARDIP = 0;
 497                         CLKOUT_FABRIC = 0;
 498                 end
 499                 else begin
 500
 501                         if(OSC_FREQ == "25k") begin
 502                                 //half period of 25 kHz
 503                                 #20000;
 504                         end
 505
 506                         else begin
 507                                 //half period of 2 MHz
 508                                 #250;
 509                         end
 510
 511                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 512                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 513                 end
 514         end
 515
 516 endmodule
 517
 518 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 519
 520         parameter PWRDN_EN = 0;
 521         parameter AUTO_PWRDN = 0;
 522         parameter HARDIP_DIV = 1;
 523         parameter FABRIC_DIV = 1;
 524
 525         initial CLKOUT_HARDIP = 0;
 526         initial CLKOUT_FABRIC = 0;
 527
 528         //output dividers not implemented for simulation
 529         //auto powerdown not implemented for simulation
 530
 531         always begin
 532                 if(PWRDN) begin
 533                         CLKOUT_HARDIP = 0;
 534                         CLKOUT_FABRIC = 0;
 535                 end
 536                 else begin
 537                         //half period of 27 MHz
 538                         #18.518;
 539                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 540                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 541                 end
 542         end
 543
 544 endmodule
 545
 546 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 547
 548         parameter OUTA_TAP = 1;
 549         parameter OUTA_INVERT = 0;
 550         parameter OUTB_TAP = 1;
 551
 552         reg[15:0] shreg = 0;
 553
 554         always @(posedge CLK, negedge nRST) begin
 555
 556                 if(!nRST)
 557                         shreg = 0;
 558
 559                 else
 560                         shreg <= {shreg[14:0], IN};
 561
 562         end
 563
 564         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
 565         assign OUTB = shreg[OUTB_TAP - 1];
 566
 567 endmodule
 568
 569 //keep constraint needed to prevent optimization since we have no outputs
 570 (* keep *)
 571 module GP_SYSRESET(input RST);
 572         parameter RESET_MODE = "EDGE";
 573         parameter EDGE_SPEED = 4;
 574
 575         //cannot simulate whole system reset
 576
 577 endmodule
 578
 579 module GP_VDD(output OUT);
 580        assign OUT = 1;
 581 endmodule
 582
 583 module GP_VREF(input VIN, output reg VOUT);
 584         parameter VIN_DIV = 1;
 585         parameter VREF = 0;
 586         //cannot simulate mixed signal IP
 587 endmodule
 588
 589 module GP_VSS(output OUT);
 590        assign OUT = 0;
 591 endmodule