techlibs/greenpak4/cells_sim.v

   1 `timescale 1ns/1ps
   2
   3 `include "cells_sim_ams.v"
   4 `include "cells_sim_digital.v"
   5
   6 //Cells still in this file have INCOMPLETE simulation models, need to finish them
   7
   8 module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
   9         parameter PWRDN_SYNC = 1'b0;
  10         parameter CLK_EDGE = "RISING";
  11         parameter GREATER_OR_EQUAL = 1'b0;
  12
  13         //TODO implement power-down mode
  14
  15         initial GREATER = 0;
  16         initial EQUAL = 0;
  17
  18         wire clk_minv = (CLK_EDGE == "RISING") ? CLK : ~CLK;
  19         always @(posedge clk_minv) begin
  20                 if(GREATER_OR_EQUAL)
  21                         GREATER <= (INP >= INN);
  22                 else
  23                         GREATER <= (INP > INN);
  24
  25                 EQUAL <= (INP == INN);
  26         end
  27
  28 endmodule
  29
  30 module GP_EDGEDET(input IN, output reg OUT);
  31
  32         parameter EDGE_DIRECTION = "RISING";
  33         parameter DELAY_STEPS = 1;
  34         parameter GLITCH_FILTER = 0;
  35
  36         //not implemented for simulation
  37
  38 endmodule
  39
  40 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
  41
  42         parameter PWRDN_EN = 0;
  43         parameter AUTO_PWRDN = 0;
  44         parameter HARDIP_DIV = 1;
  45         parameter FABRIC_DIV = 1;
  46         parameter OSC_FREQ = "25k";
  47
  48         initial CLKOUT_HARDIP = 0;
  49         initial CLKOUT_FABRIC = 0;
  50
  51         //output dividers not implemented for simulation
  52         //auto powerdown not implemented for simulation
  53
  54         always begin
  55                 if(PWRDN) begin
  56                         CLKOUT_HARDIP = 0;
  57                         CLKOUT_FABRIC = 0;
  58                 end
  59                 else begin
  60
  61                         if(OSC_FREQ == "25k") begin
  62                                 //half period of 25 kHz
  63                                 #20000;
  64                         end
  65
  66                         else begin
  67                                 //half period of 2 MHz
  68                                 #250;
  69                         end
  70
  71                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
  72                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
  73                 end
  74         end
  75
  76 endmodule
  77
  78 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
  79
  80         parameter PWRDN_EN = 0;
  81         parameter AUTO_PWRDN = 0;
  82         parameter HARDIP_DIV = 1;
  83         parameter FABRIC_DIV = 1;
  84
  85         initial CLKOUT_HARDIP = 0;
  86         initial CLKOUT_FABRIC = 0;
  87
  88         //output dividers not implemented for simulation
  89         //auto powerdown not implemented for simulation
  90
  91         always begin
  92                 if(PWRDN) begin
  93                         CLKOUT_HARDIP = 0;
  94                         CLKOUT_FABRIC = 0;
  95                 end
  96                 else begin
  97                         //half period of 27 MHz
  98                         #18.518;
  99                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 100                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 101                 end
 102         end
 103
 104 endmodule
 105
 106 module GP_SPI(
 107         input SCK,
 108         inout SDAT,
 109         input CSN,
 110         input[7:0] TXD_HIGH,
 111         input[7:0] TXD_LOW,
 112         output reg[7:0] RXD_HIGH,
 113         output reg[7:0] RXD_LOW,
 114         output reg INT);
 115
 116         initial RXD_HIGH = 0;
 117         initial RXD_LOW = 0;
 118         initial INT = 0;
 119
 120         parameter DATA_WIDTH = 8;               //byte or word width
 121         parameter SPI_CPHA = 0;                 //SPI clock phase
 122         parameter SPI_CPOL = 0;                 //SPI clock polarity
 123         parameter DIRECTION = "INPUT";  //SPI data direction (either input to chip or output to host)
 124         //parallel output to fabric not yet implemented
 125
 126         //TODO: write sim model
 127         //TODO: SPI SDIO control... can we use ADC output while SPI is input??
 128         //TODO: clock sync
 129
 130 endmodule
 131
 132 //keep constraint needed to prevent optimization since we have no outputs
 133 (* keep *)
 134 module GP_SYSRESET(input RST);
 135         parameter RESET_MODE = "EDGE";
 136         parameter EDGE_SPEED = 4;
 137
 138         //cannot simulate whole system reset
 139
 140 endmodule