techlibs/greenpak4/cells_sim.v

   1 `timescale 1ns/1ps
   2
   3 module GP_2LUT(input IN0, IN1, output OUT);
   4         parameter [3:0] INIT = 0;
   5         assign OUT = INIT[{IN1, IN0}];
   6 endmodule
   7
   8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   9         parameter [7:0] INIT = 0;
  10         assign OUT = INIT[{IN2, IN1, IN0}];
  11 endmodule
  12
  13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  14         parameter [15:0] INIT = 0;
  15         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  16 endmodule
  17
  18 module GP_ABUF(input wire IN, output wire OUT);
  19
  20         assign OUT = IN;
  21
  22         //must be 1, 5, 20, 50
  23         //values >1 only available with Vdd > 2.7V
  24         parameter BANDWIDTH_KHZ = 1;
  25
  26         //cannot simulate mixed signal IP
  27
  28 endmodule
  29
  30 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  31
  32         parameter BANDWIDTH = "HIGH";
  33         parameter VIN_ATTEN = 1;
  34         parameter VIN_ISRC_EN = 0;
  35         parameter HYSTERESIS = 0;
  36
  37         initial OUT = 0;
  38
  39         //cannot simulate mixed signal IP
  40
  41 endmodule
  42
  43 module GP_BANDGAP(output reg OK);
  44         parameter AUTO_PWRDN = 1;
  45         parameter CHOPPER_EN = 1;
  46         parameter OUT_DELAY = 100;
  47
  48         //cannot simulate mixed signal IP
  49
  50 endmodule
  51
  52 module GP_CLKBUF(input wire IN, output wire OUT);
  53         assign OUT = IN;
  54 endmodule
  55
  56 module GP_COUNT8(input CLK, input wire RST, output reg OUT, output reg[7:0] POUT);
  57
  58         parameter RESET_MODE    = "RISING";
  59
  60         parameter COUNT_TO              = 8'h1;
  61         parameter CLKIN_DIVIDE  = 1;
  62
  63         //more complex hard IP blocks are not supported for simulation yet
  64
  65         reg[7:0] count = COUNT_TO;
  66
  67         //Combinatorially output whenever we wrap low
  68         always @(*) begin
  69                 OUT <= (count == 8'h0);
  70                 OUT <= count;
  71         end
  72
  73         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  74         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  75         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  76         always @(posedge CLK) begin
  77
  78                 count           <= count - 1'd1;
  79
  80                 if(count == 0)
  81                         count   <= COUNT_TO;
  82
  83                 /*
  84                 if((RESET_MODE == "RISING") && RST)
  85                         count   <= 0;
  86                 if((RESET_MODE == "FALLING") && !RST)
  87                         count   <= 0;
  88                 if((RESET_MODE == "BOTH") && RST)
  89                         count   <= 0;
  90                 */
  91         end
  92
  93 endmodule
  94
  95 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  96
  97         parameter RESET_MODE    = "RISING";
  98
  99         parameter COUNT_TO              = 14'h1;
 100         parameter CLKIN_DIVIDE  = 1;
 101
 102         //more complex hard IP blocks are not supported for simulation yet
 103
 104 endmodule
 105
 106 module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 107                      input UP, input KEEP, output reg[7:0] POUT);
 108
 109         parameter RESET_MODE    = "RISING";
 110         parameter RESET_VALUE   = "ZERO";
 111
 112         parameter COUNT_TO              = 8'h1;
 113         parameter CLKIN_DIVIDE  = 1;
 114
 115         //more complex hard IP blocks are not supported for simulation yet
 116
 117 endmodule
 118
 119 module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 120                       input UP, input KEEP, output reg[7:0] POUT);
 121
 122         parameter RESET_MODE    = "RISING";
 123         parameter RESET_VALUE   = "ZERO";
 124
 125         parameter COUNT_TO              = 14'h1;
 126         parameter CLKIN_DIVIDE  = 1;
 127
 128         //more complex hard IP blocks are not supported for simulation yet
 129
 130 endmodule
 131
 132 module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 133
 134         initial VOUT = 0;
 135
 136         //analog hard IP is not supported for simulation
 137
 138 endmodule
 139
 140 module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
 141         parameter PWRDN_SYNC = 1'b0;
 142         parameter CLK_EDGE = "RISING";
 143         parameter GREATER_OR_EQUAL = 1'b0;
 144
 145         //TODO implement power-down mode
 146
 147         initial GREATER = 0;
 148         initial EQUAL = 0;
 149
 150         wire clk_minv = (CLK_EDGE == "RISING") ? CLK : ~CLK;
 151         always @(posedge clk_minv) begin
 152                 if(GREATER_OR_EQUAL)
 153                         GREATER <= (INP >= INN);
 154                 else
 155                         GREATER <= (INP > INN);
 156
 157                 EQUAL <= (INP == INN);
 158         end
 159
 160 endmodule
 161
 162 module GP_DCMPREF(output reg[7:0]OUT);
 163         parameter[7:0] REF_VAL = 8'h00;
 164         initial OUT = REF_VAL;
 165 endmodule
 166
 167 module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
 168
 169         always @(*) begin
 170                 case(SEL)
 171                         2'd00: begin
 172                                 OUTA <= IN0;
 173                                 OUTB <= IN3;
 174                         end
 175
 176                         2'd01: begin
 177                                 OUTA <= IN1;
 178                                 OUTB <= IN2;
 179                         end
 180
 181                         2'd02: begin
 182                                 OUTA <= IN2;
 183                                 OUTB <= IN1;
 184                         end
 185
 186                         2'd03: begin
 187                                 OUTA <= IN3;
 188                                 OUTB <= IN0;
 189                         end
 190
 191                 endcase
 192         end
 193 endmodule
 194
 195 module GP_DELAY(input IN, output reg OUT);
 196
 197         parameter DELAY_STEPS = 1;
 198         parameter GLITCH_FILTER = 0;
 199
 200         initial OUT = 0;
 201
 202         generate
 203
 204                 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
 205                 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
 206                 always @(*) begin
 207                         case(DELAY_STEPS)
 208                                 1: #166 OUT = IN;
 209                                 2: #318 OUT = IN;
 210                                 2: #471 OUT = IN;
 211                                 3: #622 OUT = IN;
 212                                 default: begin
 213                                         $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
 214                                         $finish;
 215                                 end
 216                         endcase
 217                 end
 218
 219         endgenerate
 220
 221 endmodule
 222
 223 module GP_DFF(input D, CLK, output reg Q);
 224         parameter [0:0] INIT = 1'bx;
 225         initial Q = INIT;
 226         always @(posedge CLK) begin
 227                 Q <= D;
 228         end
 229 endmodule
 230
 231 module GP_DFFI(input D, CLK, output reg nQ);
 232         parameter [0:0] INIT = 1'bx;
 233         initial nQ = INIT;
 234         always @(posedge CLK) begin
 235                 nQ <= ~D;
 236         end
 237 endmodule
 238
 239 module GP_DFFR(input D, CLK, nRST, output reg Q);
 240         parameter [0:0] INIT = 1'bx;
 241         initial Q = INIT;
 242         always @(posedge CLK, negedge nRST) begin
 243                 if (!nRST)
 244                         Q <= 1'b0;
 245                 else
 246                         Q <= D;
 247         end
 248 endmodule
 249
 250 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
 251         parameter [0:0] INIT = 1'bx;
 252         initial nQ = INIT;
 253         always @(posedge CLK, negedge nRST) begin
 254                 if (!nRST)
 255                         nQ <= 1'b1;
 256                 else
 257                         nQ <= ~D;
 258         end
 259 endmodule
 260
 261 module GP_DFFS(input D, CLK, nSET, output reg Q);
 262         parameter [0:0] INIT = 1'bx;
 263         initial Q = INIT;
 264         always @(posedge CLK, negedge nSET) begin
 265                 if (!nSET)
 266                         Q <= 1'b1;
 267                 else
 268                         Q <= D;
 269         end
 270 endmodule
 271
 272 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
 273         parameter [0:0] INIT = 1'bx;
 274         initial nQ = INIT;
 275         always @(posedge CLK, negedge nSET) begin
 276                 if (!nSET)
 277                         nQ <= 1'b0;
 278                 else
 279                         nQ <= ~D;
 280         end
 281 endmodule
 282
 283 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 284         parameter [0:0] INIT = 1'bx;
 285         parameter [0:0] SRMODE = 1'bx;
 286         initial Q = INIT;
 287         always @(posedge CLK, negedge nSR) begin
 288                 if (!nSR)
 289                         Q <= SRMODE;
 290                 else
 291                         Q <= D;
 292         end
 293 endmodule
 294
 295 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
 296         parameter [0:0] INIT = 1'bx;
 297         parameter [0:0] SRMODE = 1'bx;
 298         initial nQ = INIT;
 299         always @(posedge CLK, negedge nSR) begin
 300                 if (!nSR)
 301                         nQ <= ~SRMODE;
 302                 else
 303                         nQ <= ~D;
 304         end
 305 endmodule
 306
 307 module GP_DLATCH(input D, input nCLK, output reg Q);
 308         parameter [0:0] INIT = 1'bx;
 309         initial Q = INIT;
 310         always @(*) begin
 311                 if(!nCLK)
 312                         Q <= D;
 313         end
 314 endmodule
 315
 316 module GP_DLATCHI(input D, input nCLK, output reg nQ);
 317         parameter [0:0] INIT = 1'bx;
 318         initial nQ = INIT;
 319         always @(*) begin
 320                 if(!nCLK)
 321                         nQ <= ~D;
 322         end
 323 endmodule
 324
 325 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
 326         parameter [0:0] INIT = 1'bx;
 327         initial Q = INIT;
 328         always @(*) begin
 329                 if(!nRST)
 330                         Q <= 1'b0;
 331                 else if(!nCLK)
 332                         Q <= D;
 333         end
 334 endmodule
 335
 336 module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
 337         parameter [0:0] INIT = 1'bx;
 338         initial nQ = INIT;
 339         always @(*) begin
 340                 if(!nRST)
 341                         nQ <= 1'b1;
 342                 else if(!nCLK)
 343                         nQ <= ~D;
 344         end
 345 endmodule
 346
 347 module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
 348         parameter [0:0] INIT = 1'bx;
 349         initial Q = INIT;
 350         always @(*) begin
 351                 if(!nSET)
 352                         Q <= 1'b1;
 353                 else if(!nCLK)
 354                         Q <= D;
 355         end
 356 endmodule
 357
 358 module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
 359         parameter [0:0] INIT = 1'bx;
 360         initial nQ = INIT;
 361         always @(*) begin
 362                 if(!nSET)
 363                         nQ <= 1'b0;
 364                 else if(!nCLK)
 365                         nQ <= ~D;
 366         end
 367 endmodule
 368
 369 module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
 370         parameter [0:0] INIT = 1'bx;
 371         parameter[0:0] SRMODE = 1'bx;
 372         initial Q = INIT;
 373         always @(*) begin
 374                 if(!nSR)
 375                         Q <= SRMODE;
 376                 else if(!nCLK)
 377                         Q <= D;
 378         end
 379 endmodule
 380
 381 module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
 382         parameter [0:0] INIT = 1'bx;
 383         parameter[0:0] SRMODE = 1'bx;
 384         initial nQ = INIT;
 385         always @(*) begin
 386                 if(!nSR)
 387                         nQ <= ~SRMODE;
 388                 else if(!nCLK)
 389                         nQ <= ~D;
 390         end
 391 endmodule
 392
 393 module GP_EDGEDET(input IN, output reg OUT);
 394
 395         parameter EDGE_DIRECTION = "RISING";
 396         parameter DELAY_STEPS = 1;
 397         parameter GLITCH_FILTER = 0;
 398
 399         //not implemented for simulation
 400
 401 endmodule
 402
 403 module GP_IBUF(input IN, output OUT);
 404         assign OUT = IN;
 405 endmodule
 406
 407 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
 408         assign OUT = IO;
 409         assign IO = OE ? IN : 1'bz;
 410 endmodule
 411
 412 module GP_INV(input IN, output OUT);
 413         assign OUT = ~IN;
 414 endmodule
 415
 416 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 417
 418         parameter PWRDN_EN = 0;
 419         parameter AUTO_PWRDN = 0;
 420         parameter OUT_DIV = 1;
 421
 422         initial CLKOUT = 0;
 423
 424         //auto powerdown not implemented for simulation
 425         //output dividers not implemented for simulation
 426
 427         always begin
 428                 if(PWRDN)
 429                         CLKOUT = 0;
 430                 else begin
 431                         //half period of 1730 Hz
 432                         #289017;
 433                         CLKOUT = ~CLKOUT;
 434                 end
 435         end
 436
 437 endmodule
 438
 439 module GP_OBUF(input IN, output OUT);
 440         assign OUT = IN;
 441 endmodule
 442
 443 module GP_OBUFT(input IN, input OE, output OUT);
 444         assign OUT = OE ? IN : 1'bz;
 445 endmodule
 446
 447 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
 448
 449         parameter GAIN = 1;
 450         parameter INPUT_MODE = "SINGLE";
 451
 452         initial VOUT = 0;
 453
 454         //cannot simulate mixed signal IP
 455
 456 endmodule
 457
 458 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 459         initial OUT = 0;
 460         parameter PATTERN_DATA = 16'h0;
 461         parameter PATTERN_LEN = 5'd16;
 462
 463         reg[3:0] count = 0;
 464         always @(posedge CLK) begin
 465                 if(!nRST)
 466                         OUT <= PATTERN_DATA[0];
 467
 468                 else begin
 469                         count <= count + 1;
 470                         OUT <= PATTERN_DATA[count];
 471
 472                         if( (count + 1) == PATTERN_LEN)
 473                                 count <= 0;
 474                 end
 475         end
 476
 477 endmodule
 478
 479 module GP_PWRDET(output reg VDD_LOW);
 480         initial VDD_LOW = 0;
 481 endmodule
 482
 483 module GP_POR(output reg RST_DONE);
 484         parameter POR_TIME = 500;
 485
 486         initial begin
 487                 RST_DONE = 0;
 488
 489                 if(POR_TIME == 4)
 490                         #4000;
 491                 else if(POR_TIME == 500)
 492                         #500000;
 493                 else begin
 494                         $display("ERROR: bad POR_TIME for GP_POR cell");
 495                         $finish;
 496                 end
 497
 498                 RST_DONE = 1;
 499
 500         end
 501
 502 endmodule
 503
 504 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 505
 506         parameter PWRDN_EN = 0;
 507         parameter AUTO_PWRDN = 0;
 508         parameter HARDIP_DIV = 1;
 509         parameter FABRIC_DIV = 1;
 510         parameter OSC_FREQ = "25k";
 511
 512         initial CLKOUT_HARDIP = 0;
 513         initial CLKOUT_FABRIC = 0;
 514
 515         //output dividers not implemented for simulation
 516         //auto powerdown not implemented for simulation
 517
 518         always begin
 519                 if(PWRDN) begin
 520                         CLKOUT_HARDIP = 0;
 521                         CLKOUT_FABRIC = 0;
 522                 end
 523                 else begin
 524
 525                         if(OSC_FREQ == "25k") begin
 526                                 //half period of 25 kHz
 527                                 #20000;
 528                         end
 529
 530                         else begin
 531                                 //half period of 2 MHz
 532                                 #250;
 533                         end
 534
 535                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 536                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 537                 end
 538         end
 539
 540 endmodule
 541
 542 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 543
 544         parameter PWRDN_EN = 0;
 545         parameter AUTO_PWRDN = 0;
 546         parameter HARDIP_DIV = 1;
 547         parameter FABRIC_DIV = 1;
 548
 549         initial CLKOUT_HARDIP = 0;
 550         initial CLKOUT_FABRIC = 0;
 551
 552         //output dividers not implemented for simulation
 553         //auto powerdown not implemented for simulation
 554
 555         always begin
 556                 if(PWRDN) begin
 557                         CLKOUT_HARDIP = 0;
 558                         CLKOUT_FABRIC = 0;
 559                 end
 560                 else begin
 561                         //half period of 27 MHz
 562                         #18.518;
 563                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 564                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 565                 end
 566         end
 567
 568 endmodule
 569
 570 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 571
 572         parameter OUTA_TAP = 1;
 573         parameter OUTA_INVERT = 0;
 574         parameter OUTB_TAP = 1;
 575
 576         reg[15:0] shreg = 0;
 577
 578         always @(posedge CLK, negedge nRST) begin
 579
 580                 if(!nRST)
 581                         shreg = 0;
 582
 583                 else
 584                         shreg <= {shreg[14:0], IN};
 585
 586         end
 587
 588         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
 589         assign OUTB = shreg[OUTB_TAP - 1];
 590
 591 endmodule
 592
 593 module GP_SPI(
 594         input SCK,
 595         inout SDAT,
 596         input CSN,
 597         input[7:0] TXD_HIGH,
 598         input[7:0] TXD_LOW,
 599         output reg[7:0] RXD_HIGH,
 600         output reg[7:0] RXD_LOW,
 601         output reg INT);
 602
 603         initial DOUT_HIGH = 0;
 604         initial DOUT_LOW = 0;
 605         initial INT = 0;
 606
 607         parameter DATA_WIDTH = 8;               //byte or word width
 608         parameter SPI_CPHA = 0;                 //SPI clock phase
 609         parameter SPI_CPOL = 0;                 //SPI clock polarity
 610         parameter DIRECTION = "INPUT";  //SPI data direction (either input to chip or output to host)
 611         //parallel output to fabric not yet implemented
 612
 613         //TODO: write sim model
 614         //TODO: SPI SDIO control... can we use ADC output while SPI is input??
 615         //TODO: clock sync
 616
 617 endmodule
 618
 619 //keep constraint needed to prevent optimization since we have no outputs
 620 (* keep *)
 621 module GP_SYSRESET(input RST);
 622         parameter RESET_MODE = "EDGE";
 623         parameter EDGE_SPEED = 4;
 624
 625         //cannot simulate whole system reset
 626
 627 endmodule
 628
 629 module GP_VDD(output OUT);
 630        assign OUT = 1;
 631 endmodule
 632
 633 module GP_VREF(input VIN, output reg VOUT);
 634         parameter VIN_DIV = 1;
 635         parameter VREF = 0;
 636         //cannot simulate mixed signal IP
 637 endmodule
 638
 639 module GP_VSS(output OUT);
 640        assign OUT = 0;
 641 endmodule