3 module GP_2LUT(input IN0, IN1, output OUT);
4 parameter [3:0] INIT = 0;
5 assign OUT = INIT[{IN1, IN0}];
8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
9 parameter [7:0] INIT = 0;
10 assign OUT = INIT[{IN2, IN1, IN0}];
13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
14 parameter [15:0] INIT = 0;
15 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
18 module GP_ABUF(input wire IN, output wire OUT);
22 //must be 1, 5, 20, 50
23 //values >1 only available with Vdd > 2.7V
24 parameter BANDWIDTH_KHZ = 1;
26 //cannot simulate mixed signal IP
30 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
32 parameter BANDWIDTH = "HIGH";
33 parameter VIN_ATTEN = 1;
34 parameter VIN_ISRC_EN = 0;
35 parameter HYSTERESIS = 0;
39 //cannot simulate mixed signal IP
43 module GP_BANDGAP(output reg OK);
44 parameter AUTO_PWRDN = 1;
45 parameter CHOPPER_EN = 1;
46 parameter OUT_DELAY = 100;
48 //cannot simulate mixed signal IP
52 module GP_CLKBUF(input wire IN, output wire OUT);
56 module GP_COUNT8(input CLK, input wire RST, output reg OUT, output reg[7:0] POUT);
58 parameter RESET_MODE = "RISING";
60 parameter COUNT_TO = 8'h1;
61 parameter CLKIN_DIVIDE = 1;
63 //more complex hard IP blocks are not supported for simulation yet
65 reg[7:0] count = COUNT_TO;
67 //Combinatorially output whenever we wrap low
69 OUT <= (count == 8'h0);
73 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
74 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
75 //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
76 always @(posedge CLK) begin
78 count <= count - 1'd1;
84 if((RESET_MODE == "RISING") && RST)
86 if((RESET_MODE == "FALLING") && !RST)
88 if((RESET_MODE == "BOTH") && RST)
95 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
97 parameter RESET_MODE = "RISING";
99 parameter COUNT_TO = 14'h1;
100 parameter CLKIN_DIVIDE = 1;
102 //more complex hard IP blocks are not supported for simulation yet
106 module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
107 input UP, input KEEP, output reg[7:0] POUT);
109 parameter RESET_MODE = "RISING";
110 parameter RESET_VALUE = "ZERO";
112 parameter COUNT_TO = 8'h1;
113 parameter CLKIN_DIVIDE = 1;
115 //more complex hard IP blocks are not supported for simulation yet
119 module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
120 input UP, input KEEP, output reg[7:0] POUT);
122 parameter RESET_MODE = "RISING";
123 parameter RESET_VALUE = "ZERO";
125 parameter COUNT_TO = 14'h1;
126 parameter CLKIN_DIVIDE = 1;
128 //more complex hard IP blocks are not supported for simulation yet
132 module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
136 //analog hard IP is not supported for simulation
140 module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
141 parameter PWRDN_SYNC = 1'b0;
142 parameter CLK_EDGE = "RISING";
143 parameter GREATER_OR_EQUAL = 1'b0;
145 //TODO implement power-down mode
150 wire clk_minv = (CLK_EDGE == "RISING") ? CLK : ~CLK;
151 always @(posedge clk_minv) begin
153 GREATER <= (INP >= INN);
155 GREATER <= (INP > INN);
157 EQUAL <= (INP == INN);
162 module GP_DCMPREF(output reg[7:0]OUT);
163 parameter[7:0] REF_VAL = 8'h00;
164 initial OUT = REF_VAL;
167 module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
195 module GP_DELAY(input IN, output reg OUT);
197 parameter DELAY_STEPS = 1;
198 parameter GLITCH_FILTER = 0;
204 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
205 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
213 $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
223 module GP_DFF(input D, CLK, output reg Q);
224 parameter [0:0] INIT = 1'bx;
226 always @(posedge CLK) begin
231 module GP_DFFI(input D, CLK, output reg nQ);
232 parameter [0:0] INIT = 1'bx;
234 always @(posedge CLK) begin
239 module GP_DFFR(input D, CLK, nRST, output reg Q);
240 parameter [0:0] INIT = 1'bx;
242 always @(posedge CLK, negedge nRST) begin
250 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
251 parameter [0:0] INIT = 1'bx;
253 always @(posedge CLK, negedge nRST) begin
261 module GP_DFFS(input D, CLK, nSET, output reg Q);
262 parameter [0:0] INIT = 1'bx;
264 always @(posedge CLK, negedge nSET) begin
272 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
273 parameter [0:0] INIT = 1'bx;
275 always @(posedge CLK, negedge nSET) begin
283 module GP_DFFSR(input D, CLK, nSR, output reg Q);
284 parameter [0:0] INIT = 1'bx;
285 parameter [0:0] SRMODE = 1'bx;
287 always @(posedge CLK, negedge nSR) begin
295 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
296 parameter [0:0] INIT = 1'bx;
297 parameter [0:0] SRMODE = 1'bx;
299 always @(posedge CLK, negedge nSR) begin
307 module GP_DLATCH(input D, input nCLK, output reg Q);
308 parameter [0:0] INIT = 1'bx;
316 module GP_DLATCHI(input D, input nCLK, output reg nQ);
317 parameter [0:0] INIT = 1'bx;
325 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
326 parameter [0:0] INIT = 1'bx;
336 module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
337 parameter [0:0] INIT = 1'bx;
347 module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
348 parameter [0:0] INIT = 1'bx;
358 module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
359 parameter [0:0] INIT = 1'bx;
369 module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
370 parameter [0:0] INIT = 1'bx;
371 parameter[0:0] SRMODE = 1'bx;
381 module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
382 parameter [0:0] INIT = 1'bx;
383 parameter[0:0] SRMODE = 1'bx;
393 module GP_EDGEDET(input IN, output reg OUT);
395 parameter EDGE_DIRECTION = "RISING";
396 parameter DELAY_STEPS = 1;
397 parameter GLITCH_FILTER = 0;
399 //not implemented for simulation
403 module GP_IBUF(input IN, output OUT);
407 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
409 assign IO = OE ? IN : 1'bz;
412 module GP_INV(input IN, output OUT);
416 module GP_LFOSC(input PWRDN, output reg CLKOUT);
418 parameter PWRDN_EN = 0;
419 parameter AUTO_PWRDN = 0;
420 parameter OUT_DIV = 1;
424 //auto powerdown not implemented for simulation
425 //output dividers not implemented for simulation
431 //half period of 1730 Hz
439 module GP_OBUF(input IN, output OUT);
443 module GP_OBUFT(input IN, input OE, output OUT);
444 assign OUT = OE ? IN : 1'bz;
447 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
450 parameter INPUT_MODE = "SINGLE";
454 //cannot simulate mixed signal IP
458 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
460 parameter PATTERN_DATA = 16'h0;
461 parameter PATTERN_LEN = 5'd16;
464 always @(posedge CLK) begin
466 OUT <= PATTERN_DATA[0];
470 OUT <= PATTERN_DATA[count];
472 if( (count + 1) == PATTERN_LEN)
479 module GP_PWRDET(output reg VDD_LOW);
483 module GP_POR(output reg RST_DONE);
484 parameter POR_TIME = 500;
491 else if(POR_TIME == 500)
494 $display("ERROR: bad POR_TIME for GP_POR cell");
504 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
506 parameter PWRDN_EN = 0;
507 parameter AUTO_PWRDN = 0;
508 parameter HARDIP_DIV = 1;
509 parameter FABRIC_DIV = 1;
510 parameter OSC_FREQ = "25k";
512 initial CLKOUT_HARDIP = 0;
513 initial CLKOUT_FABRIC = 0;
515 //output dividers not implemented for simulation
516 //auto powerdown not implemented for simulation
525 if(OSC_FREQ == "25k") begin
526 //half period of 25 kHz
531 //half period of 2 MHz
535 CLKOUT_HARDIP = ~CLKOUT_HARDIP;
536 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
542 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
544 parameter PWRDN_EN = 0;
545 parameter AUTO_PWRDN = 0;
546 parameter HARDIP_DIV = 1;
547 parameter FABRIC_DIV = 1;
549 initial CLKOUT_HARDIP = 0;
550 initial CLKOUT_FABRIC = 0;
552 //output dividers not implemented for simulation
553 //auto powerdown not implemented for simulation
561 //half period of 27 MHz
563 CLKOUT_HARDIP = ~CLKOUT_HARDIP;
564 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
570 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
572 parameter OUTA_TAP = 1;
573 parameter OUTA_INVERT = 0;
574 parameter OUTB_TAP = 1;
578 always @(posedge CLK, negedge nRST) begin
584 shreg <= {shreg[14:0], IN};
588 assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
589 assign OUTB = shreg[OUTB_TAP - 1];
599 output reg[7:0] RXD_HIGH,
600 output reg[7:0] RXD_LOW,
603 initial DOUT_HIGH = 0;
604 initial DOUT_LOW = 0;
607 parameter DATA_WIDTH = 8; //byte or word width
608 parameter SPI_CPHA = 0; //SPI clock phase
609 parameter SPI_CPOL = 0; //SPI clock polarity
610 parameter DIRECTION = "INPUT"; //SPI data direction (either input to chip or output to host)
611 //parallel output to fabric not yet implemented
613 //TODO: write sim model
614 //TODO: SPI SDIO control... can we use ADC output while SPI is input??
619 //keep constraint needed to prevent optimization since we have no outputs
621 module GP_SYSRESET(input RST);
622 parameter RESET_MODE = "EDGE";
623 parameter EDGE_SPEED = 4;
625 //cannot simulate whole system reset
629 module GP_VDD(output OUT);
633 module GP_VREF(input VIN, output reg VOUT);
634 parameter VIN_DIV = 1;
636 //cannot simulate mixed signal IP
639 module GP_VSS(output OUT);