techlibs/greenpak4/cells_sim.v

   1 module GP_2LUT(input IN0, IN1, output OUT);
   2         parameter [3:0] INIT = 0;
   3         assign OUT = INIT[{IN1, IN0}];
   4 endmodule
   5
   6 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   7         parameter [7:0] INIT = 0;
   8         assign OUT = INIT[{IN2, IN1, IN0}];
   9 endmodule
  10
  11 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  12         parameter [15:0] INIT = 0;
  13         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  14 endmodule
  15
  16 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  17
  18         parameter BANDWIDTH = "HIGH";
  19         parameter VIN_BUF_EN = 0;
  20         parameter VIN_ATTEN = 1;
  21         parameter VIN_ISRC_EN = 0;
  22         parameter HYSTERESIS = 0;
  23
  24         initial OUT = 0;
  25
  26         //cannot simulate mixed signal IP
  27
  28 endmodule
  29
  30 module GP_BANDGAP(output reg OK, output reg VOUT);
  31         parameter AUTO_PWRDN = 1;
  32         parameter CHOPPER_EN = 1;
  33         parameter OUT_DELAY = 100;
  34
  35         //cannot simulate mixed signal IP
  36
  37 endmodule
  38
  39 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  40
  41         parameter RESET_MODE    = "RISING";
  42
  43         parameter COUNT_TO              = 8'h1;
  44         parameter CLKIN_DIVIDE  = 1;
  45
  46         //more complex hard IP blocks are not supported for simulation yet
  47
  48         reg[7:0] count = COUNT_TO;
  49
  50         //Combinatorially output whenever we wrap low
  51         always @(*) begin
  52                 OUT <= (count == 8'h0);
  53         end
  54
  55         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  56         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  57         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  58         always @(posedge CLK) begin
  59
  60                 count           <= count - 1'd1;
  61
  62                 if(count == 0)
  63                         count   <= COUNT_MAX;
  64
  65                 /*
  66                 if((RESET_MODE == "RISING") && RST)
  67                         count   <= 0;
  68                 if((RESET_MODE == "FALLING") && !RST)
  69                         count   <= 0;
  70                 if((RESET_MODE == "BOTH") && RST)
  71                         count   <= 0;
  72                 */
  73         end
  74
  75 endmodule
  76
  77 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  78
  79         parameter RESET_MODE    = "RISING";
  80
  81         parameter COUNT_TO              = 14'h1;
  82         parameter CLKIN_DIVIDE  = 1;
  83
  84         //more complex hard IP blocks are not supported for simulation yet
  85
  86 endmodule
  87
  88 module GP_DFF(input D, CLK, output reg Q);
  89         parameter [0:0] INIT = 1'bx;
  90         initial Q = INIT;
  91         always @(posedge CLK) begin
  92                 Q <= D;
  93         end
  94 endmodule
  95
  96 module GP_DFFR(input D, CLK, nRST, output reg Q);
  97         parameter [0:0] INIT = 1'bx;
  98         initial Q = INIT;
  99         always @(posedge CLK, negedge nRST) begin
 100                 if (!nRST)
 101                         Q <= 1'b0;
 102                 else
 103                         Q <= D;
 104         end
 105 endmodule
 106
 107 module GP_DFFS(input D, CLK, nSET, output reg Q);
 108         parameter [0:0] INIT = 1'bx;
 109         initial Q = INIT;
 110         always @(posedge CLK, negedge nSET) begin
 111                 if (!nSET)
 112                         Q <= 1'b1;
 113                 else
 114                         Q <= D;
 115         end
 116 endmodule
 117
 118 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 119         parameter [0:0] INIT = 1'bx;
 120         parameter [0:0] SRMODE = 1'bx;
 121         initial Q = INIT;
 122         always @(posedge CLK, negedge nSR) begin
 123                 if (!nSR)
 124                         Q <= SRMODE;
 125                 else
 126                         Q <= D;
 127         end
 128 endmodule
 129
 130 module GP_INV(input IN, output OUT);
 131         assign OUT = ~IN;
 132 endmodule
 133
 134 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 135
 136         parameter PWRDN_EN = 0;
 137         parameter AUTO_PWRDN = 0;
 138         parameter OUT_DIV = 1;
 139
 140         initial CLKOUT = 0;
 141
 142         //auto powerdown not implemented for simulation
 143         //output dividers not implemented for simulation
 144
 145         always begin
 146                 if(PWRDN)
 147                         CLKOUT = 0;
 148                 else begin
 149                         //half period of 1730 Hz
 150                         #289017;
 151                         CLKOUT = ~CLKOUT;
 152                 end
 153         end
 154
 155 endmodule
 156
 157 module GP_POR(output reg RST_DONE);
 158         parameter POR_TIME = 500;
 159
 160         initial begin
 161                 RST_DONE = 0;
 162
 163                 if(POR_TIME == 4)
 164                         #4000;
 165                 else if(POR_TIME == 500)
 166                         #500000;
 167                 else begin
 168                         $display("ERROR: bad POR_TIME for GP_POR cell");
 169                         $finish;
 170                 end
 171
 172                 RST_DONE = 1;
 173
 174         end
 175
 176 endmodule
 177
 178 module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 179
 180         parameter PWRDN_EN = 0;
 181         parameter AUTO_PWRDN = 0;
 182         parameter PRE_DIV = 1;
 183         parameter FABRIC_DIV = 1;
 184         parameter OSC_FREQ = "25k";
 185
 186         initial CLKOUT_PREDIV = 0;
 187         initial CLKOUT_FABRIC = 0;
 188
 189         //output dividers not implemented for simulation
 190         //auto powerdown not implemented for simulation
 191
 192         always begin
 193                 if(PWRDN) begin
 194                         CLKOUT_PREDIV = 0;
 195                         CLKOUT_FABRIC = 0;
 196                 end
 197                 else begin
 198
 199                         if(OSC_FREQ == "25k") begin
 200                                 //half period of 25 kHz
 201                                 #20000;
 202                         end
 203
 204                         else begin
 205                                 //half period of 2 MHz
 206                                 #250;
 207                         end
 208
 209                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 210                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 211                 end
 212         end
 213
 214 endmodule
 215
 216 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 217
 218         parameter PWRDN_EN = 0;
 219         parameter AUTO_PWRDN = 0;
 220         parameter PRE_DIV = 1;
 221         parameter FABRIC_DIV = 1;
 222
 223         initial CLKOUT_PREDIV = 0;
 224         initial CLKOUT_FABRIC = 0;
 225
 226         //output dividers not implemented for simulation
 227         //auto powerdown not implemented for simulation
 228
 229         always begin
 230                 if(PWRDN) begin
 231                         CLKOUT_PREDIV = 0;
 232                         CLKOUT_FABRIC = 0;
 233                 end
 234                 else begin
 235                         //half period of 27 MHz
 236                         #18.518;
 237                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 238                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 239                 end
 240         end
 241
 242 endmodule
 243
 244 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 245
 246         parameter OUTA_DELAY = 1;
 247         parameter OUTA_INVERT = 0;
 248         parameter OUTB_DELAY = 1;
 249
 250         reg[15:0] shreg = 0;
 251
 252         always @(posedge clk, negedge nRST) begin
 253
 254                 if(!nRST)
 255                         shreg = 0;
 256
 257                 else
 258                         shreg <= {shreg[14:0], IN};
 259
 260         end
 261
 262         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1];
 263         assign OUTB = shreg[OUTB_DELAY - 1];
 264
 265 endmodule
 266
 267 //keep constraint needed to prevent optimization since we have no outputs
 268 (* keep *)
 269 module GP_SYSRESET(input RST);
 270         parameter RESET_MODE = "RISING";
 271
 272         //cannot simulate whole system reset
 273
 274 endmodule
 275
 276 module GP_VDD(output OUT);
 277        assign OUT = 1;
 278 endmodule
 279
 280 module GP_VREF(input VIN, output reg VOUT);
 281         parameter VIN_DIV = 1;
 282         parameter VREF = 0;
 283         //cannot simulate mixed signal IP
 284 endmodule
 285
 286 module GP_VSS(output OUT);
 287        assign OUT = 0;
 288 endmodule