1 module GP_2LUT(input IN0, IN1, output OUT);
2 parameter [3:0] INIT = 0;
3 assign OUT = INIT[{IN1, IN0}];
6 module GP_3LUT(input IN0, IN1, IN2, output OUT);
7 parameter [7:0] INIT = 0;
8 assign OUT = INIT[{IN2, IN1, IN0}];
11 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
12 parameter [15:0] INIT = 0;
13 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
16 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
18 parameter BANDWIDTH = "HIGH";
19 parameter VIN_BUF_EN = 0;
20 parameter VIN_ATTEN = 1;
21 parameter VIN_ISRC_EN = 0;
22 parameter HYSTERESIS = 0;
26 //cannot simulate mixed signal IP
30 module GP_BANDGAP(output reg OK, output reg VOUT);
31 parameter AUTO_PWRDN = 1;
32 parameter CHOPPER_EN = 1;
33 parameter OUT_DELAY = 100;
35 //cannot simulate mixed signal IP
39 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
41 parameter RESET_MODE = "RISING";
43 parameter COUNT_TO = 8'h1;
44 parameter CLKIN_DIVIDE = 1;
46 //more complex hard IP blocks are not supported for simulation yet
48 reg[7:0] count = COUNT_TO;
50 //Combinatorially output whenever we wrap low
52 OUT <= (count == 8'h0);
55 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
56 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
57 //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
58 always @(posedge CLK) begin
60 count <= count - 1'd1;
66 if((RESET_MODE == "RISING") && RST)
68 if((RESET_MODE == "FALLING") && !RST)
70 if((RESET_MODE == "BOTH") && RST)
77 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
79 parameter RESET_MODE = "RISING";
81 parameter COUNT_TO = 14'h1;
82 parameter CLKIN_DIVIDE = 1;
84 //more complex hard IP blocks are not supported for simulation yet
88 module GP_DFF(input D, CLK, output reg Q);
89 parameter [0:0] INIT = 1'bx;
91 always @(posedge CLK) begin
96 module GP_DFFR(input D, CLK, nRST, output reg Q);
97 parameter [0:0] INIT = 1'bx;
99 always @(posedge CLK, negedge nRST) begin
107 module GP_DFFS(input D, CLK, nSET, output reg Q);
108 parameter [0:0] INIT = 1'bx;
110 always @(posedge CLK, negedge nSET) begin
118 module GP_DFFSR(input D, CLK, nSR, output reg Q);
119 parameter [0:0] INIT = 1'bx;
120 parameter [0:0] SRMODE = 1'bx;
122 always @(posedge CLK, negedge nSR) begin
130 module GP_INV(input IN, output OUT);
134 module GP_LFOSC(input PWRDN, output reg CLKOUT);
136 parameter PWRDN_EN = 0;
137 parameter AUTO_PWRDN = 0;
138 parameter OUT_DIV = 1;
142 //auto powerdown not implemented for simulation
143 //output dividers not implemented for simulation
149 //half period of 1730 Hz
157 module GP_POR(output reg RST_DONE);
158 parameter POR_TIME = 500;
165 else if(POR_TIME == 500)
168 $display("ERROR: bad POR_TIME for GP_POR cell");
178 module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
180 parameter PWRDN_EN = 0;
181 parameter AUTO_PWRDN = 0;
182 parameter PRE_DIV = 1;
183 parameter FABRIC_DIV = 1;
184 parameter OSC_FREQ = "25k";
186 initial CLKOUT_PREDIV = 0;
187 initial CLKOUT_FABRIC = 0;
189 //output dividers not implemented for simulation
190 //auto powerdown not implemented for simulation
199 if(OSC_FREQ == "25k") begin
200 //half period of 25 kHz
205 //half period of 2 MHz
209 CLKOUT_PREDIV = ~CLKOUT_PREDIV;
210 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
216 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
218 parameter PWRDN_EN = 0;
219 parameter AUTO_PWRDN = 0;
220 parameter PRE_DIV = 1;
221 parameter FABRIC_DIV = 1;
223 initial CLKOUT_PREDIV = 0;
224 initial CLKOUT_FABRIC = 0;
226 //output dividers not implemented for simulation
227 //auto powerdown not implemented for simulation
235 //half period of 27 MHz
237 CLKOUT_PREDIV = ~CLKOUT_PREDIV;
238 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
244 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
246 parameter OUTA_DELAY = 1;
247 parameter OUTA_INVERT = 0;
248 parameter OUTB_DELAY = 1;
252 always @(posedge clk, negedge nRST) begin
258 shreg <= {shreg[14:0], IN};
262 assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1];
263 assign OUTB = shreg[OUTB_DELAY - 1];
267 //keep constraint needed to prevent optimization since we have no outputs
269 module GP_SYSRESET(input RST);
270 parameter RESET_MODE = "RISING";
272 //cannot simulate whole system reset
276 module GP_VDD(output OUT);
280 module GP_VREF(input VIN, output reg VOUT);
281 parameter VIN_DIV = 1;
283 //cannot simulate mixed signal IP
286 module GP_VSS(output OUT);