techlibs/greenpak4/cells_sim.v

   1 `timescale 1ns/1ps
   2
   3 module GP_2LUT(input IN0, IN1, output OUT);
   4         parameter [3:0] INIT = 0;
   5         assign OUT = INIT[{IN1, IN0}];
   6 endmodule
   7
   8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   9         parameter [7:0] INIT = 0;
  10         assign OUT = INIT[{IN2, IN1, IN0}];
  11 endmodule
  12
  13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  14         parameter [15:0] INIT = 0;
  15         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  16 endmodule
  17
  18 module GP_ABUF(input wire IN, output wire OUT);
  19
  20         assign OUT = IN;
  21
  22         //must be 1, 5, 20, 50
  23         //values >1 only available with Vdd > 2.7V
  24         parameter BANDWIDTH_KHZ = 1;
  25
  26         //cannot simulate mixed signal IP
  27
  28 endmodule
  29
  30 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  31
  32         parameter BANDWIDTH = "HIGH";
  33         parameter VIN_ATTEN = 1;
  34         parameter VIN_ISRC_EN = 0;
  35         parameter HYSTERESIS = 0;
  36
  37         initial OUT = 0;
  38
  39         //cannot simulate mixed signal IP
  40
  41 endmodule
  42
  43 module GP_BANDGAP(output reg OK);
  44         parameter AUTO_PWRDN = 1;
  45         parameter CHOPPER_EN = 1;
  46         parameter OUT_DELAY = 100;
  47
  48         //cannot simulate mixed signal IP
  49
  50 endmodule
  51
  52 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  53
  54         parameter RESET_MODE    = "RISING";
  55
  56         parameter COUNT_TO              = 8'h1;
  57         parameter CLKIN_DIVIDE  = 1;
  58
  59         //more complex hard IP blocks are not supported for simulation yet
  60
  61         reg[7:0] count = COUNT_TO;
  62
  63         //Combinatorially output whenever we wrap low
  64         always @(*) begin
  65                 OUT <= (count == 8'h0);
  66         end
  67
  68         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  69         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  70         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  71         always @(posedge CLK) begin
  72
  73                 count           <= count - 1'd1;
  74
  75                 if(count == 0)
  76                         count   <= COUNT_TO;
  77
  78                 /*
  79                 if((RESET_MODE == "RISING") && RST)
  80                         count   <= 0;
  81                 if((RESET_MODE == "FALLING") && !RST)
  82                         count   <= 0;
  83                 if((RESET_MODE == "BOTH") && RST)
  84                         count   <= 0;
  85                 */
  86         end
  87
  88 endmodule
  89
  90 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  91
  92         parameter RESET_MODE    = "RISING";
  93
  94         parameter COUNT_TO              = 14'h1;
  95         parameter CLKIN_DIVIDE  = 1;
  96
  97         //more complex hard IP blocks are not supported for simulation yet
  98
  99 endmodule
 100
 101 module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 102                      input UP, input KEEP);
 103
 104         parameter RESET_MODE    = "RISING";
 105         parameter RESET_VALUE   = "ZERO";
 106
 107         parameter COUNT_TO              = 8'h1;
 108         parameter CLKIN_DIVIDE  = 1;
 109
 110         //more complex hard IP blocks are not supported for simulation yet
 111
 112 endmodule
 113
 114 module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 115                       input UP, input KEEP);
 116
 117         parameter RESET_MODE    = "RISING";
 118         parameter RESET_VALUE   = "ZERO";
 119
 120         parameter COUNT_TO              = 14'h1;
 121         parameter CLKIN_DIVIDE  = 1;
 122
 123         //more complex hard IP blocks are not supported for simulation yet
 124
 125 endmodule
 126
 127 module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 128
 129         initial VOUT = 0;
 130
 131         //analog hard IP is not supported for simulation
 132
 133 endmodule
 134
 135 module GP_DCMPREF(output OUT);
 136         parameter[7:0] REF_VAL = 8'h00;
 137         wire[7:0] OUT = REF_VAL;
 138 endmodule
 139
 140 module GP_DCMPMUX(input SEL, input IN0, input IN1, input IN2, input IN3, output OUT);
 141         wire[1:0] SEL;
 142         wire[7:0] IN0;
 143         wire[7:0] IN1;
 144         wire[7:0] IN2;
 145         wire[7:0] IN3;
 146         reg[7:0] OUT;
 147
 148         always @(*) begin
 149                 case(SEL)
 150                         2'b00: OUT <= IN0;
 151                         2'b10: OUT <= IN1;
 152                         2'b01: OUT <= IN2;
 153                         2'b11: OUT <= IN3;
 154                 end
 155         end
 156 endmodule
 157
 158 module GP_DELAY(input IN, output reg OUT);
 159
 160         parameter DELAY_STEPS = 1;
 161         parameter GLITCH_FILTER = 0;
 162
 163         initial OUT = 0;
 164
 165         generate
 166
 167                 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
 168                 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
 169                 always @(*) begin
 170                         case(DELAY_STEPS)
 171                                 1: #166 OUT = IN;
 172                                 2: #318 OUT = IN;
 173                                 2: #471 OUT = IN;
 174                                 3: #622 OUT = IN;
 175                                 default: begin
 176                                         $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
 177                                         $finish;
 178                                 end
 179                         endcase
 180                 end
 181
 182         endgenerate
 183
 184 endmodule
 185
 186 module GP_DFF(input D, CLK, output reg Q);
 187         parameter [0:0] INIT = 1'bx;
 188         initial Q = INIT;
 189         always @(posedge CLK) begin
 190                 Q <= D;
 191         end
 192 endmodule
 193
 194 module GP_DFFI(input D, CLK, output reg nQ);
 195         parameter [0:0] INIT = 1'bx;
 196         initial nQ = INIT;
 197         always @(posedge CLK) begin
 198                 nQ <= ~D;
 199         end
 200 endmodule
 201
 202 module GP_DFFR(input D, CLK, nRST, output reg Q);
 203         parameter [0:0] INIT = 1'bx;
 204         initial Q = INIT;
 205         always @(posedge CLK, negedge nRST) begin
 206                 if (!nRST)
 207                         Q <= 1'b0;
 208                 else
 209                         Q <= D;
 210         end
 211 endmodule
 212
 213 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
 214         parameter [0:0] INIT = 1'bx;
 215         initial nQ = INIT;
 216         always @(posedge CLK, negedge nRST) begin
 217                 if (!nRST)
 218                         nQ <= 1'b1;
 219                 else
 220                         nQ <= ~D;
 221         end
 222 endmodule
 223
 224 module GP_DFFS(input D, CLK, nSET, output reg Q);
 225         parameter [0:0] INIT = 1'bx;
 226         initial Q = INIT;
 227         always @(posedge CLK, negedge nSET) begin
 228                 if (!nSET)
 229                         Q <= 1'b1;
 230                 else
 231                         Q <= D;
 232         end
 233 endmodule
 234
 235 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
 236         parameter [0:0] INIT = 1'bx;
 237         initial nQ = INIT;
 238         always @(posedge CLK, negedge nSET) begin
 239                 if (!nSET)
 240                         nQ <= 1'b0;
 241                 else
 242                         nQ <= ~D;
 243         end
 244 endmodule
 245
 246 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 247         parameter [0:0] INIT = 1'bx;
 248         parameter [0:0] SRMODE = 1'bx;
 249         initial Q = INIT;
 250         always @(posedge CLK, negedge nSR) begin
 251                 if (!nSR)
 252                         Q <= SRMODE;
 253                 else
 254                         Q <= D;
 255         end
 256 endmodule
 257
 258 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
 259         parameter [0:0] INIT = 1'bx;
 260         parameter [0:0] SRMODE = 1'bx;
 261         initial nQ = INIT;
 262         always @(posedge CLK, negedge nSR) begin
 263                 if (!nSR)
 264                         nQ <= ~SRMODE;
 265                 else
 266                         nQ <= ~D;
 267         end
 268 endmodule
 269
 270 module GP_DLATCH(input D, input nCLK, output reg Q);
 271         parameter [0:0] INIT = 1'bx;
 272         initial Q = INIT;
 273         always @(*) begin
 274                 if(!nCLK)
 275                         Q <= D;
 276         end
 277 endmodule
 278
 279 module GP_DLATCHI(input D, input nCLK, output reg nQ);
 280         parameter [0:0] INIT = 1'bx;
 281         initial nQ = INIT;
 282         always @(*) begin
 283                 if(!nCLK)
 284                         nQ <= ~D;
 285         end
 286 endmodule
 287
 288 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
 289         parameter [0:0] INIT = 1'bx;
 290         initial Q = INIT;
 291         always @(*) begin
 292                 if(!nRST)
 293                         Q <= 1'b0;
 294                 else if(!nCLK)
 295                         Q <= D;
 296         end
 297 endmodule
 298
 299 module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
 300         parameter [0:0] INIT = 1'bx;
 301         initial nQ = INIT;
 302         always @(*) begin
 303                 if(!nRST)
 304                         nQ <= 1'b1;
 305                 else if(!nCLK)
 306                         nQ <= ~D;
 307         end
 308 endmodule
 309
 310 module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
 311         parameter [0:0] INIT = 1'bx;
 312         initial Q = INIT;
 313         always @(*) begin
 314                 if(!nSET)
 315                         Q <= 1'b1;
 316                 else if(!nCLK)
 317                         Q <= D;
 318         end
 319 endmodule
 320
 321 module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
 322         parameter [0:0] INIT = 1'bx;
 323         initial nQ = INIT;
 324         always @(*) begin
 325                 if(!nSET)
 326                         nQ <= 1'b0;
 327                 else if(!nCLK)
 328                         nQ <= ~D;
 329         end
 330 endmodule
 331
 332 module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
 333         parameter [0:0] INIT = 1'bx;
 334         parameter[0:0] SRMODE = 1'bx;
 335         initial Q = INIT;
 336         always @(*) begin
 337                 if(!nSR)
 338                         Q <= SRMODE;
 339                 else if(!nCLK)
 340                         Q <= D;
 341         end
 342 endmodule
 343
 344 module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
 345         parameter [0:0] INIT = 1'bx;
 346         parameter[0:0] SRMODE = 1'bx;
 347         initial nQ = INIT;
 348         always @(*) begin
 349                 if(!nSR)
 350                         nQ <= ~SRMODE;
 351                 else if(!nCLK)
 352                         nQ <= ~D;
 353         end
 354 endmodule
 355
 356 module GP_EDGEDET(input IN, output reg OUT);
 357
 358         parameter EDGE_DIRECTION = "RISING";
 359         parameter DELAY_STEPS = 1;
 360         parameter GLITCH_FILTER = 0;
 361
 362         //not implemented for simulation
 363
 364 endmodule
 365
 366 module GP_IBUF(input IN, output OUT);
 367         assign OUT = IN;
 368 endmodule
 369
 370 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
 371         assign OUT = IO;
 372         assign IO = OE ? IN : 1'bz;
 373 endmodule
 374
 375 module GP_INV(input IN, output OUT);
 376         assign OUT = ~IN;
 377 endmodule
 378
 379 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 380
 381         parameter PWRDN_EN = 0;
 382         parameter AUTO_PWRDN = 0;
 383         parameter OUT_DIV = 1;
 384
 385         initial CLKOUT = 0;
 386
 387         //auto powerdown not implemented for simulation
 388         //output dividers not implemented for simulation
 389
 390         always begin
 391                 if(PWRDN)
 392                         CLKOUT = 0;
 393                 else begin
 394                         //half period of 1730 Hz
 395                         #289017;
 396                         CLKOUT = ~CLKOUT;
 397                 end
 398         end
 399
 400 endmodule
 401
 402 module GP_OBUF(input IN, output OUT);
 403         assign OUT = IN;
 404 endmodule
 405
 406 module GP_OBUFT(input IN, input OE, output OUT);
 407         assign OUT = OE ? IN : 1'bz;
 408 endmodule
 409
 410 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
 411
 412         parameter GAIN = 1;
 413         parameter INPUT_MODE = "SINGLE";
 414
 415         initial VOUT = 0;
 416
 417         //cannot simulate mixed signal IP
 418
 419 endmodule
 420
 421 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 422         initial OUT = 0;
 423         parameter PATTERN_DATA = 16'h0;
 424         parameter PATTERN_LEN = 5'd16;
 425
 426         reg[3:0] count = 0;
 427         always @(posedge CLK) begin
 428                 if(!nRST)
 429                         OUT <= PATTERN_DATA[0];
 430
 431                 else begin
 432                         count <= count + 1;
 433                         OUT <= PATTERN_DATA[count];
 434
 435                         if( (count + 1) == PATTERN_LEN)
 436                                 count <= 0;
 437                 end
 438         end
 439
 440 endmodule
 441
 442 module GP_PWRDET(output reg VDD_LOW);
 443         initial VDD_LOW = 0;
 444 endmodule
 445
 446 module GP_POR(output reg RST_DONE);
 447         parameter POR_TIME = 500;
 448
 449         initial begin
 450                 RST_DONE = 0;
 451
 452                 if(POR_TIME == 4)
 453                         #4000;
 454                 else if(POR_TIME == 500)
 455                         #500000;
 456                 else begin
 457                         $display("ERROR: bad POR_TIME for GP_POR cell");
 458                         $finish;
 459                 end
 460
 461                 RST_DONE = 1;
 462
 463         end
 464
 465 endmodule
 466
 467 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 468
 469         parameter PWRDN_EN = 0;
 470         parameter AUTO_PWRDN = 0;
 471         parameter HARDIP_DIV = 1;
 472         parameter FABRIC_DIV = 1;
 473         parameter OSC_FREQ = "25k";
 474
 475         initial CLKOUT_HARDIP = 0;
 476         initial CLKOUT_FABRIC = 0;
 477
 478         //output dividers not implemented for simulation
 479         //auto powerdown not implemented for simulation
 480
 481         always begin
 482                 if(PWRDN) begin
 483                         CLKOUT_HARDIP = 0;
 484                         CLKOUT_FABRIC = 0;
 485                 end
 486                 else begin
 487
 488                         if(OSC_FREQ == "25k") begin
 489                                 //half period of 25 kHz
 490                                 #20000;
 491                         end
 492
 493                         else begin
 494                                 //half period of 2 MHz
 495                                 #250;
 496                         end
 497
 498                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 499                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 500                 end
 501         end
 502
 503 endmodule
 504
 505 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 506
 507         parameter PWRDN_EN = 0;
 508         parameter AUTO_PWRDN = 0;
 509         parameter HARDIP_DIV = 1;
 510         parameter FABRIC_DIV = 1;
 511
 512         initial CLKOUT_HARDIP = 0;
 513         initial CLKOUT_FABRIC = 0;
 514
 515         //output dividers not implemented for simulation
 516         //auto powerdown not implemented for simulation
 517
 518         always begin
 519                 if(PWRDN) begin
 520                         CLKOUT_HARDIP = 0;
 521                         CLKOUT_FABRIC = 0;
 522                 end
 523                 else begin
 524                         //half period of 27 MHz
 525                         #18.518;
 526                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 527                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 528                 end
 529         end
 530
 531 endmodule
 532
 533 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 534
 535         parameter OUTA_TAP = 1;
 536         parameter OUTA_INVERT = 0;
 537         parameter OUTB_TAP = 1;
 538
 539         reg[15:0] shreg = 0;
 540
 541         always @(posedge CLK, negedge nRST) begin
 542
 543                 if(!nRST)
 544                         shreg = 0;
 545
 546                 else
 547                         shreg <= {shreg[14:0], IN};
 548
 549         end
 550
 551         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
 552         assign OUTB = shreg[OUTB_TAP - 1];
 553
 554 endmodule
 555
 556 //keep constraint needed to prevent optimization since we have no outputs
 557 (* keep *)
 558 module GP_SYSRESET(input RST);
 559         parameter RESET_MODE = "EDGE";
 560         parameter EDGE_SPEED = 4;
 561
 562         //cannot simulate whole system reset
 563
 564 endmodule
 565
 566 module GP_VDD(output OUT);
 567        assign OUT = 1;
 568 endmodule
 569
 570 module GP_VREF(input VIN, output reg VOUT);
 571         parameter VIN_DIV = 1;
 572         parameter VREF = 0;
 573         //cannot simulate mixed signal IP
 574 endmodule
 575
 576 module GP_VSS(output OUT);
 577        assign OUT = 0;
 578 endmodule