techlibs/greenpak4/cells_sim.v

   1 `timescale 1ns/1ps
   2
   3 module GP_2LUT(input IN0, IN1, output OUT);
   4         parameter [3:0] INIT = 0;
   5         assign OUT = INIT[{IN1, IN0}];
   6 endmodule
   7
   8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   9         parameter [7:0] INIT = 0;
  10         assign OUT = INIT[{IN2, IN1, IN0}];
  11 endmodule
  12
  13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  14         parameter [15:0] INIT = 0;
  15         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  16 endmodule
  17
  18 module GP_ABUF(input wire IN, output wire OUT);
  19
  20         assign OUT = IN;
  21
  22         //cannot simulate mixed signal IP
  23
  24 endmodule
  25
  26 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  27
  28         parameter BANDWIDTH = "HIGH";
  29         parameter VIN_ATTEN = 1;
  30         parameter VIN_ISRC_EN = 0;
  31         parameter HYSTERESIS = 0;
  32
  33         initial OUT = 0;
  34
  35         //cannot simulate mixed signal IP
  36
  37 endmodule
  38
  39 module GP_BANDGAP(output reg OK);
  40         parameter AUTO_PWRDN = 1;
  41         parameter CHOPPER_EN = 1;
  42         parameter OUT_DELAY = 100;
  43
  44         //cannot simulate mixed signal IP
  45
  46 endmodule
  47
  48 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  49
  50         parameter RESET_MODE    = "RISING";
  51
  52         parameter COUNT_TO              = 8'h1;
  53         parameter CLKIN_DIVIDE  = 1;
  54
  55         //more complex hard IP blocks are not supported for simulation yet
  56
  57         reg[7:0] count = COUNT_TO;
  58
  59         //Combinatorially output whenever we wrap low
  60         always @(*) begin
  61                 OUT <= (count == 8'h0);
  62         end
  63
  64         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  65         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  66         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  67         always @(posedge CLK) begin
  68
  69                 count           <= count - 1'd1;
  70
  71                 if(count == 0)
  72                         count   <= COUNT_TO;
  73
  74                 /*
  75                 if((RESET_MODE == "RISING") && RST)
  76                         count   <= 0;
  77                 if((RESET_MODE == "FALLING") && !RST)
  78                         count   <= 0;
  79                 if((RESET_MODE == "BOTH") && RST)
  80                         count   <= 0;
  81                 */
  82         end
  83
  84 endmodule
  85
  86 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  87
  88         parameter RESET_MODE    = "RISING";
  89
  90         parameter COUNT_TO              = 14'h1;
  91         parameter CLKIN_DIVIDE  = 1;
  92
  93         //more complex hard IP blocks are not supported for simulation yet
  94
  95 endmodule
  96
  97 module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
  98                      input UP, input KEEP);
  99
 100         parameter RESET_MODE    = "RISING";
 101         parameter RESET_VALUE   = "ZERO";
 102
 103         parameter COUNT_TO              = 8'h1;
 104         parameter CLKIN_DIVIDE  = 1;
 105
 106         //more complex hard IP blocks are not supported for simulation yet
 107
 108 endmodule
 109
 110 module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 111                       input UP, input KEEP);
 112
 113         parameter RESET_MODE    = "RISING";
 114         parameter RESET_VALUE   = "ZERO";
 115
 116         parameter COUNT_TO              = 14'h1;
 117         parameter CLKIN_DIVIDE  = 1;
 118
 119         //more complex hard IP blocks are not supported for simulation yet
 120
 121 endmodule
 122
 123 module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 124
 125         initial VOUT = 0;
 126
 127         //analog hard IP is not supported for simulation
 128
 129 endmodule
 130
 131 module GP_DELAY(input IN, output reg OUT);
 132
 133         parameter DELAY_STEPS = 1;
 134         parameter GLITCH_FILTER = 0;
 135
 136         initial OUT = 0;
 137
 138         generate
 139
 140                 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
 141                 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
 142                 always @(*) begin
 143                         case(DELAY_STEPS)
 144                                 1: #166 OUT = IN;
 145                                 2: #318 OUT = IN;
 146                                 2: #471 OUT = IN;
 147                                 3: #622 OUT = IN;
 148                                 default: begin
 149                                         $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
 150                                         $finish;
 151                                 end
 152                         endcase
 153                 end
 154
 155         endgenerate
 156
 157 endmodule
 158
 159 module GP_DFF(input D, CLK, output reg Q);
 160         parameter [0:0] INIT = 1'bx;
 161         initial Q = INIT;
 162         always @(posedge CLK) begin
 163                 Q <= D;
 164         end
 165 endmodule
 166
 167 module GP_DFFI(input D, CLK, output reg nQ);
 168         parameter [0:0] INIT = 1'bx;
 169         initial nQ = INIT;
 170         always @(posedge CLK) begin
 171                 nQ <= ~D;
 172         end
 173 endmodule
 174
 175 module GP_DFFR(input D, CLK, nRST, output reg Q);
 176         parameter [0:0] INIT = 1'bx;
 177         initial Q = INIT;
 178         always @(posedge CLK, negedge nRST) begin
 179                 if (!nRST)
 180                         Q <= 1'b0;
 181                 else
 182                         Q <= D;
 183         end
 184 endmodule
 185
 186 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
 187         parameter [0:0] INIT = 1'bx;
 188         initial nQ = INIT;
 189         always @(posedge CLK, negedge nRST) begin
 190                 if (!nRST)
 191                         nQ <= 1'b1;
 192                 else
 193                         nQ <= ~D;
 194         end
 195 endmodule
 196
 197 module GP_DFFS(input D, CLK, nSET, output reg Q);
 198         parameter [0:0] INIT = 1'bx;
 199         initial Q = INIT;
 200         always @(posedge CLK, negedge nSET) begin
 201                 if (!nSET)
 202                         Q <= 1'b1;
 203                 else
 204                         Q <= D;
 205         end
 206 endmodule
 207
 208 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
 209         parameter [0:0] INIT = 1'bx;
 210         initial nQ = INIT;
 211         always @(posedge CLK, negedge nSET) begin
 212                 if (!nSET)
 213                         nQ <= 1'b0;
 214                 else
 215                         nQ <= ~D;
 216         end
 217 endmodule
 218
 219 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 220         parameter [0:0] INIT = 1'bx;
 221         parameter [0:0] SRMODE = 1'bx;
 222         initial Q = INIT;
 223         always @(posedge CLK, negedge nSR) begin
 224                 if (!nSR)
 225                         Q <= SRMODE;
 226                 else
 227                         Q <= D;
 228         end
 229 endmodule
 230
 231 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
 232         parameter [0:0] INIT = 1'bx;
 233         parameter [0:0] SRMODE = 1'bx;
 234         initial nQ = INIT;
 235         always @(posedge CLK, negedge nSR) begin
 236                 if (!nSR)
 237                         nQ <= ~SRMODE;
 238                 else
 239                         nQ <= ~D;
 240         end
 241 endmodule
 242
 243 module GP_EDGEDET(input IN, output reg OUT);
 244
 245         parameter EDGE_DIRECTION = "RISING";
 246         parameter DELAY_STEPS = 1;
 247         parameter GLITCH_FILTER = 0;
 248
 249         //not implemented for simulation
 250
 251 endmodule
 252
 253 module GP_IBUF(input IN, output OUT);
 254         assign OUT = IN;
 255 endmodule
 256
 257 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
 258         assign OUT = IO;
 259         assign IO = OE ? IN : 1'bz;
 260 endmodule
 261
 262 module GP_INV(input IN, output OUT);
 263         assign OUT = ~IN;
 264 endmodule
 265
 266 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 267
 268         parameter PWRDN_EN = 0;
 269         parameter AUTO_PWRDN = 0;
 270         parameter OUT_DIV = 1;
 271
 272         initial CLKOUT = 0;
 273
 274         //auto powerdown not implemented for simulation
 275         //output dividers not implemented for simulation
 276
 277         always begin
 278                 if(PWRDN)
 279                         CLKOUT = 0;
 280                 else begin
 281                         //half period of 1730 Hz
 282                         #289017;
 283                         CLKOUT = ~CLKOUT;
 284                 end
 285         end
 286
 287 endmodule
 288
 289 module GP_OBUF(input IN, output OUT);
 290         assign OUT = IN;
 291 endmodule
 292
 293 module GP_OBUFT(input IN, input OE, output OUT);
 294         assign OUT = OE ? IN : 1'bz;
 295 endmodule
 296
 297 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
 298
 299         parameter GAIN = 1;
 300         parameter INPUT_MODE = "SINGLE";
 301
 302         initial VOUT = 0;
 303
 304         //cannot simulate mixed signal IP
 305
 306 endmodule
 307
 308 module GP_POR(output reg RST_DONE);
 309         parameter POR_TIME = 500;
 310
 311         initial begin
 312                 RST_DONE = 0;
 313
 314                 if(POR_TIME == 4)
 315                         #4000;
 316                 else if(POR_TIME == 500)
 317                         #500000;
 318                 else begin
 319                         $display("ERROR: bad POR_TIME for GP_POR cell");
 320                         $finish;
 321                 end
 322
 323                 RST_DONE = 1;
 324
 325         end
 326
 327 endmodule
 328
 329 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 330
 331         parameter PWRDN_EN = 0;
 332         parameter AUTO_PWRDN = 0;
 333         parameter HARDIP_DIV = 1;
 334         parameter FABRIC_DIV = 1;
 335         parameter OSC_FREQ = "25k";
 336
 337         initial CLKOUT_HARDIP = 0;
 338         initial CLKOUT_FABRIC = 0;
 339
 340         //output dividers not implemented for simulation
 341         //auto powerdown not implemented for simulation
 342
 343         always begin
 344                 if(PWRDN) begin
 345                         CLKOUT_HARDIP = 0;
 346                         CLKOUT_FABRIC = 0;
 347                 end
 348                 else begin
 349
 350                         if(OSC_FREQ == "25k") begin
 351                                 //half period of 25 kHz
 352                                 #20000;
 353                         end
 354
 355                         else begin
 356                                 //half period of 2 MHz
 357                                 #250;
 358                         end
 359
 360                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 361                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 362                 end
 363         end
 364
 365 endmodule
 366
 367 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 368
 369         parameter PWRDN_EN = 0;
 370         parameter AUTO_PWRDN = 0;
 371         parameter HARDIP_DIV = 1;
 372         parameter FABRIC_DIV = 1;
 373
 374         initial CLKOUT_HARDIP = 0;
 375         initial CLKOUT_FABRIC = 0;
 376
 377         //output dividers not implemented for simulation
 378         //auto powerdown not implemented for simulation
 379
 380         always begin
 381                 if(PWRDN) begin
 382                         CLKOUT_HARDIP = 0;
 383                         CLKOUT_FABRIC = 0;
 384                 end
 385                 else begin
 386                         //half period of 27 MHz
 387                         #18.518;
 388                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 389                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 390                 end
 391         end
 392
 393 endmodule
 394
 395 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 396
 397         parameter OUTA_TAP = 1;
 398         parameter OUTA_INVERT = 0;
 399         parameter OUTB_TAP = 1;
 400
 401         reg[15:0] shreg = 0;
 402
 403         always @(posedge CLK, negedge nRST) begin
 404
 405                 if(!nRST)
 406                         shreg = 0;
 407
 408                 else
 409                         shreg <= {shreg[14:0], IN};
 410
 411         end
 412
 413         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
 414         assign OUTB = shreg[OUTB_TAP - 1];
 415
 416 endmodule
 417
 418 //keep constraint needed to prevent optimization since we have no outputs
 419 (* keep *)
 420 module GP_SYSRESET(input RST);
 421         parameter RESET_MODE = "EDGE";
 422         parameter EDGE_SPEED = 4;
 423
 424         //cannot simulate whole system reset
 425
 426 endmodule
 427
 428 module GP_VDD(output OUT);
 429        assign OUT = 1;
 430 endmodule
 431
 432 module GP_VREF(input VIN, output reg VOUT);
 433         parameter VIN_DIV = 1;
 434         parameter VREF = 0;
 435         //cannot simulate mixed signal IP
 436 endmodule
 437
 438 module GP_VSS(output OUT);
 439        assign OUT = 0;
 440 endmodule