techlibs/greenpak4/cells_sim.v

   1 `timescale 1ns/1ps
   2
   3 module GP_2LUT(input IN0, IN1, output OUT);
   4         parameter [3:0] INIT = 0;
   5         assign OUT = INIT[{IN1, IN0}];
   6 endmodule
   7
   8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   9         parameter [7:0] INIT = 0;
  10         assign OUT = INIT[{IN2, IN1, IN0}];
  11 endmodule
  12
  13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  14         parameter [15:0] INIT = 0;
  15         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  16 endmodule
  17
  18 module GP_ABUF(input wire IN, output wire OUT);
  19
  20         assign OUT = IN;
  21
  22         //cannot simulate mixed signal IP
  23
  24 endmodule
  25
  26 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  27
  28         parameter BANDWIDTH = "HIGH";
  29         parameter VIN_ATTEN = 1;
  30         parameter VIN_ISRC_EN = 0;
  31         parameter HYSTERESIS = 0;
  32
  33         initial OUT = 0;
  34
  35         //cannot simulate mixed signal IP
  36
  37 endmodule
  38
  39 module GP_BANDGAP(output reg OK);
  40         parameter AUTO_PWRDN = 1;
  41         parameter CHOPPER_EN = 1;
  42         parameter OUT_DELAY = 100;
  43
  44         //cannot simulate mixed signal IP
  45
  46 endmodule
  47
  48 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  49
  50         parameter RESET_MODE    = "RISING";
  51
  52         parameter COUNT_TO              = 8'h1;
  53         parameter CLKIN_DIVIDE  = 1;
  54
  55         //more complex hard IP blocks are not supported for simulation yet
  56
  57         reg[7:0] count = COUNT_TO;
  58
  59         //Combinatorially output whenever we wrap low
  60         always @(*) begin
  61                 OUT <= (count == 8'h0);
  62         end
  63
  64         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  65         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  66         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  67         always @(posedge CLK) begin
  68
  69                 count           <= count - 1'd1;
  70
  71                 if(count == 0)
  72                         count   <= COUNT_TO;
  73
  74                 /*
  75                 if((RESET_MODE == "RISING") && RST)
  76                         count   <= 0;
  77                 if((RESET_MODE == "FALLING") && !RST)
  78                         count   <= 0;
  79                 if((RESET_MODE == "BOTH") && RST)
  80                         count   <= 0;
  81                 */
  82         end
  83
  84 endmodule
  85
  86 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  87
  88         parameter RESET_MODE    = "RISING";
  89
  90         parameter COUNT_TO              = 14'h1;
  91         parameter CLKIN_DIVIDE  = 1;
  92
  93         //more complex hard IP blocks are not supported for simulation yet
  94
  95 endmodule
  96
  97 module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
  98                      input UP, input KEEP);
  99
 100         parameter RESET_MODE    = "RISING";
 101         parameter RESET_VALUE   = "ZERO";
 102
 103         parameter COUNT_TO              = 8'h1;
 104         parameter CLKIN_DIVIDE  = 1;
 105
 106         //more complex hard IP blocks are not supported for simulation yet
 107
 108 endmodule
 109
 110 module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 111                       input UP, input KEEP);
 112
 113         parameter RESET_MODE    = "RISING";
 114         parameter RESET_VALUE   = "ZERO";
 115
 116         parameter COUNT_TO              = 14'h1;
 117         parameter CLKIN_DIVIDE  = 1;
 118
 119         //more complex hard IP blocks are not supported for simulation yet
 120
 121 endmodule
 122
 123 module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 124
 125         initial VOUT = 0;
 126
 127         //analog hard IP is not supported for simulation
 128
 129 endmodule
 130
 131 module GP_DELAY(input IN, output reg OUT);
 132
 133         parameter DELAY_STEPS = 1;
 134
 135         //TODO: additional delay/glitch filter mode
 136
 137         initial OUT = 0;
 138
 139         generate
 140
 141                 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
 142                 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
 143                 always @(*) begin
 144                         case(DELAY_STEPS)
 145                                 1: #166 OUT = IN;
 146                                 2: #318 OUT = IN;
 147                                 2: #471 OUT = IN;
 148                                 3: #622 OUT = IN;
 149                                 default: begin
 150                                         $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
 151                                         $finish;
 152                                 end
 153                         endcase
 154                 end
 155
 156         endgenerate
 157
 158 endmodule
 159
 160 module GP_DFF(input D, CLK, output reg Q);
 161         parameter [0:0] INIT = 1'bx;
 162         initial Q = INIT;
 163         always @(posedge CLK) begin
 164                 Q <= D;
 165         end
 166 endmodule
 167
 168 module GP_DFFI(input D, CLK, output reg nQ);
 169         parameter [0:0] INIT = 1'bx;
 170         initial nQ = INIT;
 171         always @(posedge CLK) begin
 172                 nQ <= ~D;
 173         end
 174 endmodule
 175
 176 module GP_DFFR(input D, CLK, nRST, output reg Q);
 177         parameter [0:0] INIT = 1'bx;
 178         initial Q = INIT;
 179         always @(posedge CLK, negedge nRST) begin
 180                 if (!nRST)
 181                         Q <= 1'b0;
 182                 else
 183                         Q <= D;
 184         end
 185 endmodule
 186
 187 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
 188         parameter [0:0] INIT = 1'bx;
 189         initial nQ = INIT;
 190         always @(posedge CLK, negedge nRST) begin
 191                 if (!nRST)
 192                         nQ <= 1'b1;
 193                 else
 194                         nQ <= ~D;
 195         end
 196 endmodule
 197
 198 module GP_DFFS(input D, CLK, nSET, output reg Q);
 199         parameter [0:0] INIT = 1'bx;
 200         initial Q = INIT;
 201         always @(posedge CLK, negedge nSET) begin
 202                 if (!nSET)
 203                         Q <= 1'b1;
 204                 else
 205                         Q <= D;
 206         end
 207 endmodule
 208
 209 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
 210         parameter [0:0] INIT = 1'bx;
 211         initial nQ = INIT;
 212         always @(posedge CLK, negedge nSET) begin
 213                 if (!nSET)
 214                         nQ <= 1'b0;
 215                 else
 216                         nQ <= ~D;
 217         end
 218 endmodule
 219
 220 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 221         parameter [0:0] INIT = 1'bx;
 222         parameter [0:0] SRMODE = 1'bx;
 223         initial Q = INIT;
 224         always @(posedge CLK, negedge nSR) begin
 225                 if (!nSR)
 226                         Q <= SRMODE;
 227                 else
 228                         Q <= D;
 229         end
 230 endmodule
 231
 232 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
 233         parameter [0:0] INIT = 1'bx;
 234         parameter [0:0] SRMODE = 1'bx;
 235         initial nQ = INIT;
 236         always @(posedge CLK, negedge nSR) begin
 237                 if (!nSR)
 238                         nQ <= ~SRMODE;
 239                 else
 240                         nQ <= ~D;
 241         end
 242 endmodule
 243
 244 module GP_IBUF(input IN, output OUT);
 245         assign OUT = IN;
 246 endmodule
 247
 248 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
 249         assign OUT = IO;
 250         assign IO = OE ? IN : 1'bz;
 251 endmodule
 252
 253 module GP_INV(input IN, output OUT);
 254         assign OUT = ~IN;
 255 endmodule
 256
 257 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 258
 259         parameter PWRDN_EN = 0;
 260         parameter AUTO_PWRDN = 0;
 261         parameter OUT_DIV = 1;
 262
 263         initial CLKOUT = 0;
 264
 265         //auto powerdown not implemented for simulation
 266         //output dividers not implemented for simulation
 267
 268         always begin
 269                 if(PWRDN)
 270                         CLKOUT = 0;
 271                 else begin
 272                         //half period of 1730 Hz
 273                         #289017;
 274                         CLKOUT = ~CLKOUT;
 275                 end
 276         end
 277
 278 endmodule
 279
 280 module GP_OBUF(input IN, output OUT);
 281         assign OUT = IN;
 282 endmodule
 283
 284 module GP_OBUFT(input IN, input OE, output OUT);
 285         assign OUT = OE ? IN : 1'bz;
 286 endmodule
 287
 288 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
 289
 290         parameter GAIN = 1;
 291         parameter INPUT_MODE = "SINGLE";
 292
 293         initial VOUT = 0;
 294
 295         //cannot simulate mixed signal IP
 296
 297 endmodule
 298
 299 module GP_POR(output reg RST_DONE);
 300         parameter POR_TIME = 500;
 301
 302         initial begin
 303                 RST_DONE = 0;
 304
 305                 if(POR_TIME == 4)
 306                         #4000;
 307                 else if(POR_TIME == 500)
 308                         #500000;
 309                 else begin
 310                         $display("ERROR: bad POR_TIME for GP_POR cell");
 311                         $finish;
 312                 end
 313
 314                 RST_DONE = 1;
 315
 316         end
 317
 318 endmodule
 319
 320 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 321
 322         parameter PWRDN_EN = 0;
 323         parameter AUTO_PWRDN = 0;
 324         parameter HARDIP_DIV = 1;
 325         parameter FABRIC_DIV = 1;
 326         parameter OSC_FREQ = "25k";
 327
 328         initial CLKOUT_HARDIP = 0;
 329         initial CLKOUT_FABRIC = 0;
 330
 331         //output dividers not implemented for simulation
 332         //auto powerdown not implemented for simulation
 333
 334         always begin
 335                 if(PWRDN) begin
 336                         CLKOUT_HARDIP = 0;
 337                         CLKOUT_FABRIC = 0;
 338                 end
 339                 else begin
 340
 341                         if(OSC_FREQ == "25k") begin
 342                                 //half period of 25 kHz
 343                                 #20000;
 344                         end
 345
 346                         else begin
 347                                 //half period of 2 MHz
 348                                 #250;
 349                         end
 350
 351                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 352                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 353                 end
 354         end
 355
 356 endmodule
 357
 358 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 359
 360         parameter PWRDN_EN = 0;
 361         parameter AUTO_PWRDN = 0;
 362         parameter HARDIP_DIV = 1;
 363         parameter FABRIC_DIV = 1;
 364
 365         initial CLKOUT_HARDIP = 0;
 366         initial CLKOUT_FABRIC = 0;
 367
 368         //output dividers not implemented for simulation
 369         //auto powerdown not implemented for simulation
 370
 371         always begin
 372                 if(PWRDN) begin
 373                         CLKOUT_HARDIP = 0;
 374                         CLKOUT_FABRIC = 0;
 375                 end
 376                 else begin
 377                         //half period of 27 MHz
 378                         #18.518;
 379                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 380                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 381                 end
 382         end
 383
 384 endmodule
 385
 386 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 387
 388         parameter OUTA_TAP = 1;
 389         parameter OUTA_INVERT = 0;
 390         parameter OUTB_TAP = 1;
 391
 392         reg[15:0] shreg = 0;
 393
 394         always @(posedge CLK, negedge nRST) begin
 395
 396                 if(!nRST)
 397                         shreg = 0;
 398
 399                 else
 400                         shreg <= {shreg[14:0], IN};
 401
 402         end
 403
 404         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
 405         assign OUTB = shreg[OUTB_TAP - 1];
 406
 407 endmodule
 408
 409 //keep constraint needed to prevent optimization since we have no outputs
 410 (* keep *)
 411 module GP_SYSRESET(input RST);
 412         parameter RESET_MODE = "RISING";
 413
 414         //cannot simulate whole system reset
 415
 416 endmodule
 417
 418 module GP_VDD(output OUT);
 419        assign OUT = 1;
 420 endmodule
 421
 422 module GP_VREF(input VIN, output reg VOUT);
 423         parameter VIN_DIV = 1;
 424         parameter VREF = 0;
 425         //cannot simulate mixed signal IP
 426 endmodule
 427
 428 module GP_VSS(output OUT);
 429        assign OUT = 0;
 430 endmodule