techlibs/greenpak4/cells_sim.v

   1 module GP_2LUT(input IN0, IN1, output OUT);
   2         parameter [3:0] INIT = 0;
   3         assign OUT = INIT[{IN1, IN0}];
   4 endmodule
   5
   6 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   7         parameter [7:0] INIT = 0;
   8         assign OUT = INIT[{IN2, IN1, IN0}];
   9 endmodule
  10
  11 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  12         parameter [15:0] INIT = 0;
  13         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  14 endmodule
  15
  16 module GP_ABUF(input wire IN, output wire OUT);
  17
  18         assign OUT = IN;
  19
  20         //cannot simulate mixed signal IP
  21
  22 endmodule
  23
  24 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  25
  26         parameter BANDWIDTH = "HIGH";
  27         parameter VIN_ATTEN = 1;
  28         parameter VIN_ISRC_EN = 0;
  29         parameter HYSTERESIS = 0;
  30
  31         initial OUT = 0;
  32
  33         //cannot simulate mixed signal IP
  34
  35 endmodule
  36
  37 module GP_BANDGAP(output reg OK, output reg VOUT);
  38         parameter AUTO_PWRDN = 1;
  39         parameter CHOPPER_EN = 1;
  40         parameter OUT_DELAY = 100;
  41
  42         //cannot simulate mixed signal IP
  43
  44 endmodule
  45
  46 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  47
  48         parameter RESET_MODE    = "RISING";
  49
  50         parameter COUNT_TO              = 8'h1;
  51         parameter CLKIN_DIVIDE  = 1;
  52
  53         //more complex hard IP blocks are not supported for simulation yet
  54
  55         reg[7:0] count = COUNT_TO;
  56
  57         //Combinatorially output whenever we wrap low
  58         always @(*) begin
  59                 OUT <= (count == 8'h0);
  60         end
  61
  62         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  63         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  64         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  65         always @(posedge CLK) begin
  66
  67                 count           <= count - 1'd1;
  68
  69                 if(count == 0)
  70                         count   <= COUNT_MAX;
  71
  72                 /*
  73                 if((RESET_MODE == "RISING") && RST)
  74                         count   <= 0;
  75                 if((RESET_MODE == "FALLING") && !RST)
  76                         count   <= 0;
  77                 if((RESET_MODE == "BOTH") && RST)
  78                         count   <= 0;
  79                 */
  80         end
  81
  82 endmodule
  83
  84 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  85
  86         parameter RESET_MODE    = "RISING";
  87
  88         parameter COUNT_TO              = 14'h1;
  89         parameter CLKIN_DIVIDE  = 1;
  90
  91         //more complex hard IP blocks are not supported for simulation yet
  92
  93 endmodule
  94
  95 module GP_DFF(input D, CLK, output reg Q);
  96         parameter [0:0] INIT = 1'bx;
  97         initial Q = INIT;
  98         always @(posedge CLK) begin
  99                 Q <= D;
 100         end
 101 endmodule
 102
 103 module GP_DFFR(input D, CLK, nRST, output reg Q);
 104         parameter [0:0] INIT = 1'bx;
 105         initial Q = INIT;
 106         always @(posedge CLK, negedge nRST) begin
 107                 if (!nRST)
 108                         Q <= 1'b0;
 109                 else
 110                         Q <= D;
 111         end
 112 endmodule
 113
 114 module GP_DFFS(input D, CLK, nSET, output reg Q);
 115         parameter [0:0] INIT = 1'bx;
 116         initial Q = INIT;
 117         always @(posedge CLK, negedge nSET) begin
 118                 if (!nSET)
 119                         Q <= 1'b1;
 120                 else
 121                         Q <= D;
 122         end
 123 endmodule
 124
 125 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 126         parameter [0:0] INIT = 1'bx;
 127         parameter [0:0] SRMODE = 1'bx;
 128         initial Q = INIT;
 129         always @(posedge CLK, negedge nSR) begin
 130                 if (!nSR)
 131                         Q <= SRMODE;
 132                 else
 133                         Q <= D;
 134         end
 135 endmodule
 136
 137 module GP_INV(input IN, output OUT);
 138         assign OUT = ~IN;
 139 endmodule
 140
 141 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 142
 143         parameter PWRDN_EN = 0;
 144         parameter AUTO_PWRDN = 0;
 145         parameter OUT_DIV = 1;
 146
 147         initial CLKOUT = 0;
 148
 149         //auto powerdown not implemented for simulation
 150         //output dividers not implemented for simulation
 151
 152         always begin
 153                 if(PWRDN)
 154                         CLKOUT = 0;
 155                 else begin
 156                         //half period of 1730 Hz
 157                         #289017;
 158                         CLKOUT = ~CLKOUT;
 159                 end
 160         end
 161
 162 endmodule
 163
 164 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
 165
 166         parameter GAIN = 1;
 167         parameter INPUT_MODE = "SINGLE";
 168
 169         initial VOUT = 0;
 170
 171         //cannot simulate mixed signal IP
 172
 173 endmodule
 174
 175 module GP_POR(output reg RST_DONE);
 176         parameter POR_TIME = 500;
 177
 178         initial begin
 179                 RST_DONE = 0;
 180
 181                 if(POR_TIME == 4)
 182                         #4000;
 183                 else if(POR_TIME == 500)
 184                         #500000;
 185                 else begin
 186                         $display("ERROR: bad POR_TIME for GP_POR cell");
 187                         $finish;
 188                 end
 189
 190                 RST_DONE = 1;
 191
 192         end
 193
 194 endmodule
 195
 196 module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 197
 198         parameter PWRDN_EN = 0;
 199         parameter AUTO_PWRDN = 0;
 200         parameter PRE_DIV = 1;
 201         parameter FABRIC_DIV = 1;
 202         parameter OSC_FREQ = "25k";
 203
 204         initial CLKOUT_PREDIV = 0;
 205         initial CLKOUT_FABRIC = 0;
 206
 207         //output dividers not implemented for simulation
 208         //auto powerdown not implemented for simulation
 209
 210         always begin
 211                 if(PWRDN) begin
 212                         CLKOUT_PREDIV = 0;
 213                         CLKOUT_FABRIC = 0;
 214                 end
 215                 else begin
 216
 217                         if(OSC_FREQ == "25k") begin
 218                                 //half period of 25 kHz
 219                                 #20000;
 220                         end
 221
 222                         else begin
 223                                 //half period of 2 MHz
 224                                 #250;
 225                         end
 226
 227                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 228                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 229                 end
 230         end
 231
 232 endmodule
 233
 234 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 235
 236         parameter PWRDN_EN = 0;
 237         parameter AUTO_PWRDN = 0;
 238         parameter PRE_DIV = 1;
 239         parameter FABRIC_DIV = 1;
 240
 241         initial CLKOUT_PREDIV = 0;
 242         initial CLKOUT_FABRIC = 0;
 243
 244         //output dividers not implemented for simulation
 245         //auto powerdown not implemented for simulation
 246
 247         always begin
 248                 if(PWRDN) begin
 249                         CLKOUT_PREDIV = 0;
 250                         CLKOUT_FABRIC = 0;
 251                 end
 252                 else begin
 253                         //half period of 27 MHz
 254                         #18.518;
 255                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 256                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 257                 end
 258         end
 259
 260 endmodule
 261
 262 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 263
 264         parameter OUTA_DELAY = 1;
 265         parameter OUTA_INVERT = 0;
 266         parameter OUTB_DELAY = 1;
 267
 268         reg[15:0] shreg = 0;
 269
 270         always @(posedge clk, negedge nRST) begin
 271
 272                 if(!nRST)
 273                         shreg = 0;
 274
 275                 else
 276                         shreg <= {shreg[14:0], IN};
 277
 278         end
 279
 280         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1];
 281         assign OUTB = shreg[OUTB_DELAY - 1];
 282
 283 endmodule
 284
 285 //keep constraint needed to prevent optimization since we have no outputs
 286 (* keep *)
 287 module GP_SYSRESET(input RST);
 288         parameter RESET_MODE = "RISING";
 289
 290         //cannot simulate whole system reset
 291
 292 endmodule
 293
 294 module GP_VDD(output OUT);
 295        assign OUT = 1;
 296 endmodule
 297
 298 module GP_VREF(input VIN, output reg VOUT);
 299         parameter VIN_DIV = 1;
 300         parameter VREF = 0;
 301         //cannot simulate mixed signal IP
 302 endmodule
 303
 304 module GP_VSS(output OUT);
 305        assign OUT = 0;
 306 endmodule