1 module GP_2LUT(input IN0, IN1, output OUT);
2 parameter [3:0] INIT = 0;
3 assign OUT = INIT[{IN1, IN0}];
6 module GP_3LUT(input IN0, IN1, IN2, output OUT);
7 parameter [7:0] INIT = 0;
8 assign OUT = INIT[{IN2, IN1, IN0}];
11 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
12 parameter [15:0] INIT = 0;
13 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
16 module GP_ABUF(input wire IN, output wire OUT);
20 //cannot simulate mixed signal IP
24 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
26 parameter BANDWIDTH = "HIGH";
27 parameter VIN_ATTEN = 1;
28 parameter VIN_ISRC_EN = 0;
29 parameter HYSTERESIS = 0;
33 //cannot simulate mixed signal IP
37 module GP_BANDGAP(output reg OK, output reg VOUT);
38 parameter AUTO_PWRDN = 1;
39 parameter CHOPPER_EN = 1;
40 parameter OUT_DELAY = 100;
42 //cannot simulate mixed signal IP
46 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
48 parameter RESET_MODE = "RISING";
50 parameter COUNT_TO = 8'h1;
51 parameter CLKIN_DIVIDE = 1;
53 //more complex hard IP blocks are not supported for simulation yet
55 reg[7:0] count = COUNT_TO;
57 //Combinatorially output whenever we wrap low
59 OUT <= (count == 8'h0);
62 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
63 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
64 //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
65 always @(posedge CLK) begin
67 count <= count - 1'd1;
73 if((RESET_MODE == "RISING") && RST)
75 if((RESET_MODE == "FALLING") && !RST)
77 if((RESET_MODE == "BOTH") && RST)
84 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
86 parameter RESET_MODE = "RISING";
88 parameter COUNT_TO = 14'h1;
89 parameter CLKIN_DIVIDE = 1;
91 //more complex hard IP blocks are not supported for simulation yet
95 module GP_DFF(input D, CLK, output reg Q);
96 parameter [0:0] INIT = 1'bx;
98 always @(posedge CLK) begin
103 module GP_DFFR(input D, CLK, nRST, output reg Q);
104 parameter [0:0] INIT = 1'bx;
106 always @(posedge CLK, negedge nRST) begin
114 module GP_DFFS(input D, CLK, nSET, output reg Q);
115 parameter [0:0] INIT = 1'bx;
117 always @(posedge CLK, negedge nSET) begin
125 module GP_DFFSR(input D, CLK, nSR, output reg Q);
126 parameter [0:0] INIT = 1'bx;
127 parameter [0:0] SRMODE = 1'bx;
129 always @(posedge CLK, negedge nSR) begin
137 module GP_INV(input IN, output OUT);
141 module GP_LFOSC(input PWRDN, output reg CLKOUT);
143 parameter PWRDN_EN = 0;
144 parameter AUTO_PWRDN = 0;
145 parameter OUT_DIV = 1;
149 //auto powerdown not implemented for simulation
150 //output dividers not implemented for simulation
156 //half period of 1730 Hz
164 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
167 parameter INPUT_MODE = "SINGLE";
171 //cannot simulate mixed signal IP
175 module GP_POR(output reg RST_DONE);
176 parameter POR_TIME = 500;
183 else if(POR_TIME == 500)
186 $display("ERROR: bad POR_TIME for GP_POR cell");
196 module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
198 parameter PWRDN_EN = 0;
199 parameter AUTO_PWRDN = 0;
200 parameter PRE_DIV = 1;
201 parameter FABRIC_DIV = 1;
202 parameter OSC_FREQ = "25k";
204 initial CLKOUT_PREDIV = 0;
205 initial CLKOUT_FABRIC = 0;
207 //output dividers not implemented for simulation
208 //auto powerdown not implemented for simulation
217 if(OSC_FREQ == "25k") begin
218 //half period of 25 kHz
223 //half period of 2 MHz
227 CLKOUT_PREDIV = ~CLKOUT_PREDIV;
228 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
234 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
236 parameter PWRDN_EN = 0;
237 parameter AUTO_PWRDN = 0;
238 parameter PRE_DIV = 1;
239 parameter FABRIC_DIV = 1;
241 initial CLKOUT_PREDIV = 0;
242 initial CLKOUT_FABRIC = 0;
244 //output dividers not implemented for simulation
245 //auto powerdown not implemented for simulation
253 //half period of 27 MHz
255 CLKOUT_PREDIV = ~CLKOUT_PREDIV;
256 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
262 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
264 parameter OUTA_DELAY = 1;
265 parameter OUTA_INVERT = 0;
266 parameter OUTB_DELAY = 1;
270 always @(posedge clk, negedge nRST) begin
276 shreg <= {shreg[14:0], IN};
280 assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1];
281 assign OUTB = shreg[OUTB_DELAY - 1];
285 //keep constraint needed to prevent optimization since we have no outputs
287 module GP_SYSRESET(input RST);
288 parameter RESET_MODE = "RISING";
290 //cannot simulate whole system reset
294 module GP_VDD(output OUT);
298 module GP_VREF(input VIN, output reg VOUT);
299 parameter VIN_DIV = 1;
301 //cannot simulate mixed signal IP
304 module GP_VSS(output OUT);