3 module GP_2LUT(input IN0, IN1, output OUT);
4 parameter [3:0] INIT = 0;
5 assign OUT = INIT[{IN1, IN0}];
8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
9 parameter [7:0] INIT = 0;
10 assign OUT = INIT[{IN2, IN1, IN0}];
13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
14 parameter [15:0] INIT = 0;
15 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
18 module GP_ABUF(input wire IN, output wire OUT);
22 //cannot simulate mixed signal IP
26 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
28 parameter BANDWIDTH = "HIGH";
29 parameter VIN_ATTEN = 1;
30 parameter VIN_ISRC_EN = 0;
31 parameter HYSTERESIS = 0;
35 //cannot simulate mixed signal IP
39 module GP_BANDGAP(output reg OK);
40 parameter AUTO_PWRDN = 1;
41 parameter CHOPPER_EN = 1;
42 parameter OUT_DELAY = 100;
44 //cannot simulate mixed signal IP
48 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
50 parameter RESET_MODE = "RISING";
52 parameter COUNT_TO = 8'h1;
53 parameter CLKIN_DIVIDE = 1;
55 //more complex hard IP blocks are not supported for simulation yet
57 reg[7:0] count = COUNT_TO;
59 //Combinatorially output whenever we wrap low
61 OUT <= (count == 8'h0);
64 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
65 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
66 //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
67 always @(posedge CLK) begin
69 count <= count - 1'd1;
75 if((RESET_MODE == "RISING") && RST)
77 if((RESET_MODE == "FALLING") && !RST)
79 if((RESET_MODE == "BOTH") && RST)
86 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
88 parameter RESET_MODE = "RISING";
90 parameter COUNT_TO = 14'h1;
91 parameter CLKIN_DIVIDE = 1;
93 //more complex hard IP blocks are not supported for simulation yet
97 module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
98 input UP, input KEEP);
100 parameter RESET_MODE = "RISING";
101 parameter RESET_VALUE = "ZERO";
103 parameter COUNT_TO = 8'h1;
104 parameter CLKIN_DIVIDE = 1;
106 //more complex hard IP blocks are not supported for simulation yet
110 module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
111 input UP, input KEEP);
113 parameter RESET_MODE = "RISING";
114 parameter RESET_VALUE = "ZERO";
116 parameter COUNT_TO = 14'h1;
117 parameter CLKIN_DIVIDE = 1;
119 //more complex hard IP blocks are not supported for simulation yet
123 module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
127 //analog hard IP is not supported for simulation
131 module GP_DELAY(input IN, output reg OUT);
133 parameter DELAY_STEPS = 1;
134 parameter GLITCH_FILTER = 0;
140 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
141 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
149 $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
159 module GP_DFF(input D, CLK, output reg Q);
160 parameter [0:0] INIT = 1'bx;
162 always @(posedge CLK) begin
167 module GP_DFFI(input D, CLK, output reg nQ);
168 parameter [0:0] INIT = 1'bx;
170 always @(posedge CLK) begin
175 module GP_DFFR(input D, CLK, nRST, output reg Q);
176 parameter [0:0] INIT = 1'bx;
178 always @(posedge CLK, negedge nRST) begin
186 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
187 parameter [0:0] INIT = 1'bx;
189 always @(posedge CLK, negedge nRST) begin
197 module GP_DFFS(input D, CLK, nSET, output reg Q);
198 parameter [0:0] INIT = 1'bx;
200 always @(posedge CLK, negedge nSET) begin
208 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
209 parameter [0:0] INIT = 1'bx;
211 always @(posedge CLK, negedge nSET) begin
219 module GP_DFFSR(input D, CLK, nSR, output reg Q);
220 parameter [0:0] INIT = 1'bx;
221 parameter [0:0] SRMODE = 1'bx;
223 always @(posedge CLK, negedge nSR) begin
231 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
232 parameter [0:0] INIT = 1'bx;
233 parameter [0:0] SRMODE = 1'bx;
235 always @(posedge CLK, negedge nSR) begin
243 module GP_EDGEDET(input IN, output reg OUT);
245 parameter EDGE_DIRECTION = "RISING";
246 parameter DELAY_STEPS = 1;
247 parameter GLITCH_FILTER = 0;
249 //not implemented for simulation
253 module GP_IBUF(input IN, output OUT);
257 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
259 assign IO = OE ? IN : 1'bz;
262 module GP_INV(input IN, output OUT);
266 module GP_LFOSC(input PWRDN, output reg CLKOUT);
268 parameter PWRDN_EN = 0;
269 parameter AUTO_PWRDN = 0;
270 parameter OUT_DIV = 1;
274 //auto powerdown not implemented for simulation
275 //output dividers not implemented for simulation
281 //half period of 1730 Hz
289 module GP_OBUF(input IN, output OUT);
293 module GP_OBUFT(input IN, input OE, output OUT);
294 assign OUT = OE ? IN : 1'bz;
297 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
300 parameter INPUT_MODE = "SINGLE";
304 //cannot simulate mixed signal IP
308 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
310 parameter PATTERN_DATA = 16'h0;
311 parameter PATTERN_LEN = 5'd16;
314 always @(posedge CLK) begin
316 OUT <= PATTERN_DATA[0];
320 OUT <= PATTERN_DATA[count];
322 if( (count + 1) == PATTERN_LEN)
329 module GP_POR(output reg RST_DONE);
330 parameter POR_TIME = 500;
337 else if(POR_TIME == 500)
340 $display("ERROR: bad POR_TIME for GP_POR cell");
350 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
352 parameter PWRDN_EN = 0;
353 parameter AUTO_PWRDN = 0;
354 parameter HARDIP_DIV = 1;
355 parameter FABRIC_DIV = 1;
356 parameter OSC_FREQ = "25k";
358 initial CLKOUT_HARDIP = 0;
359 initial CLKOUT_FABRIC = 0;
361 //output dividers not implemented for simulation
362 //auto powerdown not implemented for simulation
371 if(OSC_FREQ == "25k") begin
372 //half period of 25 kHz
377 //half period of 2 MHz
381 CLKOUT_HARDIP = ~CLKOUT_HARDIP;
382 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
388 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
390 parameter PWRDN_EN = 0;
391 parameter AUTO_PWRDN = 0;
392 parameter HARDIP_DIV = 1;
393 parameter FABRIC_DIV = 1;
395 initial CLKOUT_HARDIP = 0;
396 initial CLKOUT_FABRIC = 0;
398 //output dividers not implemented for simulation
399 //auto powerdown not implemented for simulation
407 //half period of 27 MHz
409 CLKOUT_HARDIP = ~CLKOUT_HARDIP;
410 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
416 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
418 parameter OUTA_TAP = 1;
419 parameter OUTA_INVERT = 0;
420 parameter OUTB_TAP = 1;
424 always @(posedge CLK, negedge nRST) begin
430 shreg <= {shreg[14:0], IN};
434 assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
435 assign OUTB = shreg[OUTB_TAP - 1];
439 //keep constraint needed to prevent optimization since we have no outputs
441 module GP_SYSRESET(input RST);
442 parameter RESET_MODE = "EDGE";
443 parameter EDGE_SPEED = 4;
445 //cannot simulate whole system reset
449 module GP_VDD(output OUT);
453 module GP_VREF(input VIN, output reg VOUT);
454 parameter VIN_DIV = 1;
456 //cannot simulate mixed signal IP
459 module GP_VSS(output OUT);