3 module GP_2LUT(input IN0, IN1, output OUT);
4 parameter [3:0] INIT = 0;
5 assign OUT = INIT[{IN1, IN0}];
8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
9 parameter [7:0] INIT = 0;
10 assign OUT = INIT[{IN2, IN1, IN0}];
13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
14 parameter [15:0] INIT = 0;
15 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
18 module GP_ABUF(input wire IN, output wire OUT);
22 //must be 1, 5, 20, 50
23 //values >1 only available with Vdd > 2.7V
24 parameter BANDWIDTH_KHZ = 1;
26 //cannot simulate mixed signal IP
30 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
32 parameter BANDWIDTH = "HIGH";
33 parameter VIN_ATTEN = 1;
34 parameter VIN_ISRC_EN = 0;
35 parameter HYSTERESIS = 0;
39 //cannot simulate mixed signal IP
43 module GP_BANDGAP(output reg OK);
44 parameter AUTO_PWRDN = 1;
45 parameter CHOPPER_EN = 1;
46 parameter OUT_DELAY = 100;
48 //cannot simulate mixed signal IP
52 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
54 parameter RESET_MODE = "RISING";
56 parameter COUNT_TO = 8'h1;
57 parameter CLKIN_DIVIDE = 1;
59 //more complex hard IP blocks are not supported for simulation yet
61 reg[7:0] count = COUNT_TO;
63 //Combinatorially output whenever we wrap low
65 OUT <= (count == 8'h0);
68 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
69 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
70 //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
71 always @(posedge CLK) begin
73 count <= count - 1'd1;
79 if((RESET_MODE == "RISING") && RST)
81 if((RESET_MODE == "FALLING") && !RST)
83 if((RESET_MODE == "BOTH") && RST)
90 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
92 parameter RESET_MODE = "RISING";
94 parameter COUNT_TO = 14'h1;
95 parameter CLKIN_DIVIDE = 1;
97 //more complex hard IP blocks are not supported for simulation yet
101 module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
102 input UP, input KEEP);
104 parameter RESET_MODE = "RISING";
105 parameter RESET_VALUE = "ZERO";
107 parameter COUNT_TO = 8'h1;
108 parameter CLKIN_DIVIDE = 1;
110 //more complex hard IP blocks are not supported for simulation yet
114 module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
115 input UP, input KEEP);
117 parameter RESET_MODE = "RISING";
118 parameter RESET_VALUE = "ZERO";
120 parameter COUNT_TO = 14'h1;
121 parameter CLKIN_DIVIDE = 1;
123 //more complex hard IP blocks are not supported for simulation yet
127 module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
131 //analog hard IP is not supported for simulation
135 module GP_DCMPREF(output OUT)
136 parameter[7:0] REF_VAL = 8'h00;
137 wire[7:0] OUT = REF_VAL;
140 module GP_DCMPMUX(input SEL, input IN0, input IN1, input IN2, input IN3, output OUT)
158 module GP_DELAY(input IN, output reg OUT);
160 parameter DELAY_STEPS = 1;
161 parameter GLITCH_FILTER = 0;
167 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
168 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
176 $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
186 module GP_DFF(input D, CLK, output reg Q);
187 parameter [0:0] INIT = 1'bx;
189 always @(posedge CLK) begin
194 module GP_DFFI(input D, CLK, output reg nQ);
195 parameter [0:0] INIT = 1'bx;
197 always @(posedge CLK) begin
202 module GP_DFFR(input D, CLK, nRST, output reg Q);
203 parameter [0:0] INIT = 1'bx;
205 always @(posedge CLK, negedge nRST) begin
213 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
214 parameter [0:0] INIT = 1'bx;
216 always @(posedge CLK, negedge nRST) begin
224 module GP_DFFS(input D, CLK, nSET, output reg Q);
225 parameter [0:0] INIT = 1'bx;
227 always @(posedge CLK, negedge nSET) begin
235 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
236 parameter [0:0] INIT = 1'bx;
238 always @(posedge CLK, negedge nSET) begin
246 module GP_DFFSR(input D, CLK, nSR, output reg Q);
247 parameter [0:0] INIT = 1'bx;
248 parameter [0:0] SRMODE = 1'bx;
250 always @(posedge CLK, negedge nSR) begin
258 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
259 parameter [0:0] INIT = 1'bx;
260 parameter [0:0] SRMODE = 1'bx;
262 always @(posedge CLK, negedge nSR) begin
270 module GP_DLATCH(input D, input nCLK, output reg Q);
271 parameter [0:0] INIT = 1'bx;
279 module GP_DLATCHI(input D, input nCLK, output reg nQ);
280 parameter [0:0] INIT = 1'bx;
288 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
289 parameter [0:0] INIT = 1'bx;
299 module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
300 parameter [0:0] INIT = 1'bx;
310 module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
311 parameter [0:0] INIT = 1'bx;
321 module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
322 parameter [0:0] INIT = 1'bx;
332 module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
333 parameter [0:0] INIT = 1'bx;
334 parameter[0:0] SRMODE = 1'bx;
344 module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
345 parameter [0:0] INIT = 1'bx;
346 parameter[0:0] SRMODE = 1'bx;
356 module GP_EDGEDET(input IN, output reg OUT);
358 parameter EDGE_DIRECTION = "RISING";
359 parameter DELAY_STEPS = 1;
360 parameter GLITCH_FILTER = 0;
362 //not implemented for simulation
366 module GP_IBUF(input IN, output OUT);
370 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
372 assign IO = OE ? IN : 1'bz;
375 module GP_INV(input IN, output OUT);
379 module GP_LFOSC(input PWRDN, output reg CLKOUT);
381 parameter PWRDN_EN = 0;
382 parameter AUTO_PWRDN = 0;
383 parameter OUT_DIV = 1;
387 //auto powerdown not implemented for simulation
388 //output dividers not implemented for simulation
394 //half period of 1730 Hz
402 module GP_OBUF(input IN, output OUT);
406 module GP_OBUFT(input IN, input OE, output OUT);
407 assign OUT = OE ? IN : 1'bz;
410 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
413 parameter INPUT_MODE = "SINGLE";
417 //cannot simulate mixed signal IP
421 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
423 parameter PATTERN_DATA = 16'h0;
424 parameter PATTERN_LEN = 5'd16;
427 always @(posedge CLK) begin
429 OUT <= PATTERN_DATA[0];
433 OUT <= PATTERN_DATA[count];
435 if( (count + 1) == PATTERN_LEN)
442 module GP_PWRDET(output reg VDD_LOW);
446 module GP_POR(output reg RST_DONE);
447 parameter POR_TIME = 500;
454 else if(POR_TIME == 500)
457 $display("ERROR: bad POR_TIME for GP_POR cell");
467 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
469 parameter PWRDN_EN = 0;
470 parameter AUTO_PWRDN = 0;
471 parameter HARDIP_DIV = 1;
472 parameter FABRIC_DIV = 1;
473 parameter OSC_FREQ = "25k";
475 initial CLKOUT_HARDIP = 0;
476 initial CLKOUT_FABRIC = 0;
478 //output dividers not implemented for simulation
479 //auto powerdown not implemented for simulation
488 if(OSC_FREQ == "25k") begin
489 //half period of 25 kHz
494 //half period of 2 MHz
498 CLKOUT_HARDIP = ~CLKOUT_HARDIP;
499 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
505 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
507 parameter PWRDN_EN = 0;
508 parameter AUTO_PWRDN = 0;
509 parameter HARDIP_DIV = 1;
510 parameter FABRIC_DIV = 1;
512 initial CLKOUT_HARDIP = 0;
513 initial CLKOUT_FABRIC = 0;
515 //output dividers not implemented for simulation
516 //auto powerdown not implemented for simulation
524 //half period of 27 MHz
526 CLKOUT_HARDIP = ~CLKOUT_HARDIP;
527 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
533 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
535 parameter OUTA_TAP = 1;
536 parameter OUTA_INVERT = 0;
537 parameter OUTB_TAP = 1;
541 always @(posedge CLK, negedge nRST) begin
547 shreg <= {shreg[14:0], IN};
551 assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
552 assign OUTB = shreg[OUTB_TAP - 1];
556 //keep constraint needed to prevent optimization since we have no outputs
558 module GP_SYSRESET(input RST);
559 parameter RESET_MODE = "EDGE";
560 parameter EDGE_SPEED = 4;
562 //cannot simulate whole system reset
566 module GP_VDD(output OUT);
570 module GP_VREF(input VIN, output reg VOUT);
571 parameter VIN_DIV = 1;
573 //cannot simulate mixed signal IP
576 module GP_VSS(output OUT);