techlibs/greenpak4/cells_sim.v

   1 `timescale 1ns/1ps
   2
   3 module GP_2LUT(input IN0, IN1, output OUT);
   4         parameter [3:0] INIT = 0;
   5         assign OUT = INIT[{IN1, IN0}];
   6 endmodule
   7
   8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   9         parameter [7:0] INIT = 0;
  10         assign OUT = INIT[{IN2, IN1, IN0}];
  11 endmodule
  12
  13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  14         parameter [15:0] INIT = 0;
  15         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  16 endmodule
  17
  18 module GP_ABUF(input wire IN, output wire OUT);
  19
  20         assign OUT = IN;
  21
  22         //must be 1, 5, 20, 50
  23         //values >1 only available with Vdd > 2.7V
  24         parameter BANDWIDTH_KHZ = 1;
  25
  26         //cannot simulate mixed signal IP
  27
  28 endmodule
  29
  30 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  31
  32         parameter BANDWIDTH = "HIGH";
  33         parameter VIN_ATTEN = 1;
  34         parameter VIN_ISRC_EN = 0;
  35         parameter HYSTERESIS = 0;
  36
  37         initial OUT = 0;
  38
  39         //cannot simulate mixed signal IP
  40
  41 endmodule
  42
  43 module GP_BANDGAP(output reg OK);
  44         parameter AUTO_PWRDN = 1;
  45         parameter CHOPPER_EN = 1;
  46         parameter OUT_DELAY = 100;
  47
  48         //cannot simulate mixed signal IP
  49
  50 endmodule
  51
  52 module GP_CLKBUF(input wire IN, output wire OUT);
  53         assign OUT = IN;
  54 endmodule
  55
  56 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  57
  58         parameter RESET_MODE    = "RISING";
  59
  60         parameter COUNT_TO              = 8'h1;
  61         parameter CLKIN_DIVIDE  = 1;
  62
  63         //more complex hard IP blocks are not supported for simulation yet
  64
  65         reg[7:0] count = COUNT_TO;
  66
  67         //Combinatorially output whenever we wrap low
  68         always @(*) begin
  69                 OUT <= (count == 8'h0);
  70         end
  71
  72         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  73         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  74         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  75         always @(posedge CLK) begin
  76
  77                 count           <= count - 1'd1;
  78
  79                 if(count == 0)
  80                         count   <= COUNT_TO;
  81
  82                 /*
  83                 if((RESET_MODE == "RISING") && RST)
  84                         count   <= 0;
  85                 if((RESET_MODE == "FALLING") && !RST)
  86                         count   <= 0;
  87                 if((RESET_MODE == "BOTH") && RST)
  88                         count   <= 0;
  89                 */
  90         end
  91
  92 endmodule
  93
  94 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  95
  96         parameter RESET_MODE    = "RISING";
  97
  98         parameter COUNT_TO              = 14'h1;
  99         parameter CLKIN_DIVIDE  = 1;
 100
 101         //more complex hard IP blocks are not supported for simulation yet
 102
 103 endmodule
 104
 105 module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 106                      input UP, input KEEP);
 107
 108         parameter RESET_MODE    = "RISING";
 109         parameter RESET_VALUE   = "ZERO";
 110
 111         parameter COUNT_TO              = 8'h1;
 112         parameter CLKIN_DIVIDE  = 1;
 113
 114         //more complex hard IP blocks are not supported for simulation yet
 115
 116 endmodule
 117
 118 module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 119                       input UP, input KEEP);
 120
 121         parameter RESET_MODE    = "RISING";
 122         parameter RESET_VALUE   = "ZERO";
 123
 124         parameter COUNT_TO              = 14'h1;
 125         parameter CLKIN_DIVIDE  = 1;
 126
 127         //more complex hard IP blocks are not supported for simulation yet
 128
 129 endmodule
 130
 131 module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 132
 133         initial VOUT = 0;
 134
 135         //analog hard IP is not supported for simulation
 136
 137 endmodule
 138
 139 module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
 140         parameter PWRDN_SYNC = 1'b0;
 141         parameter CLK_EDGE = "RISING";
 142         parameter GREATER_OR_EQUAL = 1'b0;
 143
 144         //TODO implement power-down mode
 145
 146         initial GREATER = 0;
 147         initial EQUAL = 0;
 148
 149         wire clk_minv = (CLK_EDGE == "RISING") ? CLK : ~CLK;
 150         always @(posedge clk_minv) begin
 151                 if(GREATER_OR_EQUAL)
 152                         GREATER <= (INP >= INN);
 153                 else
 154                         GREATER <= (INP > INN);
 155
 156                 EQUAL <= (INP == INN);
 157         end
 158
 159 endmodule
 160
 161 module GP_DCMPREF(output reg[7:0]OUT);
 162         parameter[7:0] REF_VAL = 8'h00;
 163         initial OUT = REF_VAL;
 164 endmodule
 165
 166 module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
 167
 168         always @(*) begin
 169                 case(SEL)
 170                         2'd00: begin
 171                                 OUTA <= IN0;
 172                                 OUTB <= IN3;
 173                         end
 174
 175                         2'd01: begin
 176                                 OUTA <= IN1;
 177                                 OUTB <= IN2;
 178                         end
 179
 180                         2'd02: begin
 181                                 OUTA <= IN2;
 182                                 OUTB <= IN1;
 183                         end
 184
 185                         2'd03: begin
 186                                 OUTA <= IN3;
 187                                 OUTB <= IN0;
 188                         end
 189
 190                 endcase
 191         end
 192 endmodule
 193
 194 module GP_DELAY(input IN, output reg OUT);
 195
 196         parameter DELAY_STEPS = 1;
 197         parameter GLITCH_FILTER = 0;
 198
 199         initial OUT = 0;
 200
 201         generate
 202
 203                 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
 204                 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
 205                 always @(*) begin
 206                         case(DELAY_STEPS)
 207                                 1: #166 OUT = IN;
 208                                 2: #318 OUT = IN;
 209                                 2: #471 OUT = IN;
 210                                 3: #622 OUT = IN;
 211                                 default: begin
 212                                         $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
 213                                         $finish;
 214                                 end
 215                         endcase
 216                 end
 217
 218         endgenerate
 219
 220 endmodule
 221
 222 module GP_DFF(input D, CLK, output reg Q);
 223         parameter [0:0] INIT = 1'bx;
 224         initial Q = INIT;
 225         always @(posedge CLK) begin
 226                 Q <= D;
 227         end
 228 endmodule
 229
 230 module GP_DFFI(input D, CLK, output reg nQ);
 231         parameter [0:0] INIT = 1'bx;
 232         initial nQ = INIT;
 233         always @(posedge CLK) begin
 234                 nQ <= ~D;
 235         end
 236 endmodule
 237
 238 module GP_DFFR(input D, CLK, nRST, output reg Q);
 239         parameter [0:0] INIT = 1'bx;
 240         initial Q = INIT;
 241         always @(posedge CLK, negedge nRST) begin
 242                 if (!nRST)
 243                         Q <= 1'b0;
 244                 else
 245                         Q <= D;
 246         end
 247 endmodule
 248
 249 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
 250         parameter [0:0] INIT = 1'bx;
 251         initial nQ = INIT;
 252         always @(posedge CLK, negedge nRST) begin
 253                 if (!nRST)
 254                         nQ <= 1'b1;
 255                 else
 256                         nQ <= ~D;
 257         end
 258 endmodule
 259
 260 module GP_DFFS(input D, CLK, nSET, output reg Q);
 261         parameter [0:0] INIT = 1'bx;
 262         initial Q = INIT;
 263         always @(posedge CLK, negedge nSET) begin
 264                 if (!nSET)
 265                         Q <= 1'b1;
 266                 else
 267                         Q <= D;
 268         end
 269 endmodule
 270
 271 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
 272         parameter [0:0] INIT = 1'bx;
 273         initial nQ = INIT;
 274         always @(posedge CLK, negedge nSET) begin
 275                 if (!nSET)
 276                         nQ <= 1'b0;
 277                 else
 278                         nQ <= ~D;
 279         end
 280 endmodule
 281
 282 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 283         parameter [0:0] INIT = 1'bx;
 284         parameter [0:0] SRMODE = 1'bx;
 285         initial Q = INIT;
 286         always @(posedge CLK, negedge nSR) begin
 287                 if (!nSR)
 288                         Q <= SRMODE;
 289                 else
 290                         Q <= D;
 291         end
 292 endmodule
 293
 294 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
 295         parameter [0:0] INIT = 1'bx;
 296         parameter [0:0] SRMODE = 1'bx;
 297         initial nQ = INIT;
 298         always @(posedge CLK, negedge nSR) begin
 299                 if (!nSR)
 300                         nQ <= ~SRMODE;
 301                 else
 302                         nQ <= ~D;
 303         end
 304 endmodule
 305
 306 module GP_DLATCH(input D, input nCLK, output reg Q);
 307         parameter [0:0] INIT = 1'bx;
 308         initial Q = INIT;
 309         always @(*) begin
 310                 if(!nCLK)
 311                         Q <= D;
 312         end
 313 endmodule
 314
 315 module GP_DLATCHI(input D, input nCLK, output reg nQ);
 316         parameter [0:0] INIT = 1'bx;
 317         initial nQ = INIT;
 318         always @(*) begin
 319                 if(!nCLK)
 320                         nQ <= ~D;
 321         end
 322 endmodule
 323
 324 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
 325         parameter [0:0] INIT = 1'bx;
 326         initial Q = INIT;
 327         always @(*) begin
 328                 if(!nRST)
 329                         Q <= 1'b0;
 330                 else if(!nCLK)
 331                         Q <= D;
 332         end
 333 endmodule
 334
 335 module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
 336         parameter [0:0] INIT = 1'bx;
 337         initial nQ = INIT;
 338         always @(*) begin
 339                 if(!nRST)
 340                         nQ <= 1'b1;
 341                 else if(!nCLK)
 342                         nQ <= ~D;
 343         end
 344 endmodule
 345
 346 module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
 347         parameter [0:0] INIT = 1'bx;
 348         initial Q = INIT;
 349         always @(*) begin
 350                 if(!nSET)
 351                         Q <= 1'b1;
 352                 else if(!nCLK)
 353                         Q <= D;
 354         end
 355 endmodule
 356
 357 module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
 358         parameter [0:0] INIT = 1'bx;
 359         initial nQ = INIT;
 360         always @(*) begin
 361                 if(!nSET)
 362                         nQ <= 1'b0;
 363                 else if(!nCLK)
 364                         nQ <= ~D;
 365         end
 366 endmodule
 367
 368 module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
 369         parameter [0:0] INIT = 1'bx;
 370         parameter[0:0] SRMODE = 1'bx;
 371         initial Q = INIT;
 372         always @(*) begin
 373                 if(!nSR)
 374                         Q <= SRMODE;
 375                 else if(!nCLK)
 376                         Q <= D;
 377         end
 378 endmodule
 379
 380 module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
 381         parameter [0:0] INIT = 1'bx;
 382         parameter[0:0] SRMODE = 1'bx;
 383         initial nQ = INIT;
 384         always @(*) begin
 385                 if(!nSR)
 386                         nQ <= ~SRMODE;
 387                 else if(!nCLK)
 388                         nQ <= ~D;
 389         end
 390 endmodule
 391
 392 module GP_EDGEDET(input IN, output reg OUT);
 393
 394         parameter EDGE_DIRECTION = "RISING";
 395         parameter DELAY_STEPS = 1;
 396         parameter GLITCH_FILTER = 0;
 397
 398         //not implemented for simulation
 399
 400 endmodule
 401
 402 module GP_IBUF(input IN, output OUT);
 403         assign OUT = IN;
 404 endmodule
 405
 406 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
 407         assign OUT = IO;
 408         assign IO = OE ? IN : 1'bz;
 409 endmodule
 410
 411 module GP_INV(input IN, output OUT);
 412         assign OUT = ~IN;
 413 endmodule
 414
 415 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 416
 417         parameter PWRDN_EN = 0;
 418         parameter AUTO_PWRDN = 0;
 419         parameter OUT_DIV = 1;
 420
 421         initial CLKOUT = 0;
 422
 423         //auto powerdown not implemented for simulation
 424         //output dividers not implemented for simulation
 425
 426         always begin
 427                 if(PWRDN)
 428                         CLKOUT = 0;
 429                 else begin
 430                         //half period of 1730 Hz
 431                         #289017;
 432                         CLKOUT = ~CLKOUT;
 433                 end
 434         end
 435
 436 endmodule
 437
 438 module GP_OBUF(input IN, output OUT);
 439         assign OUT = IN;
 440 endmodule
 441
 442 module GP_OBUFT(input IN, input OE, output OUT);
 443         assign OUT = OE ? IN : 1'bz;
 444 endmodule
 445
 446 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
 447
 448         parameter GAIN = 1;
 449         parameter INPUT_MODE = "SINGLE";
 450
 451         initial VOUT = 0;
 452
 453         //cannot simulate mixed signal IP
 454
 455 endmodule
 456
 457 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 458         initial OUT = 0;
 459         parameter PATTERN_DATA = 16'h0;
 460         parameter PATTERN_LEN = 5'd16;
 461
 462         reg[3:0] count = 0;
 463         always @(posedge CLK) begin
 464                 if(!nRST)
 465                         OUT <= PATTERN_DATA[0];
 466
 467                 else begin
 468                         count <= count + 1;
 469                         OUT <= PATTERN_DATA[count];
 470
 471                         if( (count + 1) == PATTERN_LEN)
 472                                 count <= 0;
 473                 end
 474         end
 475
 476 endmodule
 477
 478 module GP_PWRDET(output reg VDD_LOW);
 479         initial VDD_LOW = 0;
 480 endmodule
 481
 482 module GP_POR(output reg RST_DONE);
 483         parameter POR_TIME = 500;
 484
 485         initial begin
 486                 RST_DONE = 0;
 487
 488                 if(POR_TIME == 4)
 489                         #4000;
 490                 else if(POR_TIME == 500)
 491                         #500000;
 492                 else begin
 493                         $display("ERROR: bad POR_TIME for GP_POR cell");
 494                         $finish;
 495                 end
 496
 497                 RST_DONE = 1;
 498
 499         end
 500
 501 endmodule
 502
 503 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 504
 505         parameter PWRDN_EN = 0;
 506         parameter AUTO_PWRDN = 0;
 507         parameter HARDIP_DIV = 1;
 508         parameter FABRIC_DIV = 1;
 509         parameter OSC_FREQ = "25k";
 510
 511         initial CLKOUT_HARDIP = 0;
 512         initial CLKOUT_FABRIC = 0;
 513
 514         //output dividers not implemented for simulation
 515         //auto powerdown not implemented for simulation
 516
 517         always begin
 518                 if(PWRDN) begin
 519                         CLKOUT_HARDIP = 0;
 520                         CLKOUT_FABRIC = 0;
 521                 end
 522                 else begin
 523
 524                         if(OSC_FREQ == "25k") begin
 525                                 //half period of 25 kHz
 526                                 #20000;
 527                         end
 528
 529                         else begin
 530                                 //half period of 2 MHz
 531                                 #250;
 532                         end
 533
 534                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 535                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 536                 end
 537         end
 538
 539 endmodule
 540
 541 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 542
 543         parameter PWRDN_EN = 0;
 544         parameter AUTO_PWRDN = 0;
 545         parameter HARDIP_DIV = 1;
 546         parameter FABRIC_DIV = 1;
 547
 548         initial CLKOUT_HARDIP = 0;
 549         initial CLKOUT_FABRIC = 0;
 550
 551         //output dividers not implemented for simulation
 552         //auto powerdown not implemented for simulation
 553
 554         always begin
 555                 if(PWRDN) begin
 556                         CLKOUT_HARDIP = 0;
 557                         CLKOUT_FABRIC = 0;
 558                 end
 559                 else begin
 560                         //half period of 27 MHz
 561                         #18.518;
 562                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 563                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 564                 end
 565         end
 566
 567 endmodule
 568
 569 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 570
 571         parameter OUTA_TAP = 1;
 572         parameter OUTA_INVERT = 0;
 573         parameter OUTB_TAP = 1;
 574
 575         reg[15:0] shreg = 0;
 576
 577         always @(posedge CLK, negedge nRST) begin
 578
 579                 if(!nRST)
 580                         shreg = 0;
 581
 582                 else
 583                         shreg <= {shreg[14:0], IN};
 584
 585         end
 586
 587         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
 588         assign OUTB = shreg[OUTB_TAP - 1];
 589
 590 endmodule
 591
 592 module GP_SPI(
 593         input SCK,
 594         inout SDAT,
 595         input CSN,
 596         output reg MISO,
 597         input[7:0] TXD_HIGH,
 598         input[7:0] TXD_LOW,
 599         output reg[7:0] RXD_HIGH,
 600         output reg[7:0] RXD_LOW);
 601
 602         initial DOUT_HIGH = 0;
 603         initial DOUT_LOW = 0;
 604
 605         parameter DATA_WIDTH = 8;               //byte or word width
 606         parameter SPI_CPHA = 0;                 //SPI clock phase
 607         parameter SPI_CPOL = 0;                 //SPI clock polarity
 608         parameter DIRECTION = "INPUT";  //SPI data direction (either input to chip or output to host)
 609         //parallel output to fabric not yet implemented
 610
 611         //TODO: write sim model
 612         //TODO: SPI SDIO control... can we use ADC output while SPI is input??
 613         //TODO: clock sync
 614
 615 endmodule
 616
 617 //keep constraint needed to prevent optimization since we have no outputs
 618 (* keep *)
 619 module GP_SYSRESET(input RST);
 620         parameter RESET_MODE = "EDGE";
 621         parameter EDGE_SPEED = 4;
 622
 623         //cannot simulate whole system reset
 624
 625 endmodule
 626
 627 module GP_VDD(output OUT);
 628        assign OUT = 1;
 629 endmodule
 630
 631 module GP_VREF(input VIN, output reg VOUT);
 632         parameter VIN_DIV = 1;
 633         parameter VREF = 0;
 634         //cannot simulate mixed signal IP
 635 endmodule
 636
 637 module GP_VSS(output OUT);
 638        assign OUT = 0;
 639 endmodule