techlibs/greenpak4/cells_sim.v

   1 `timescale 1ns/1ps
   2
   3 module GP_2LUT(input IN0, IN1, output OUT);
   4         parameter [3:0] INIT = 0;
   5         assign OUT = INIT[{IN1, IN0}];
   6 endmodule
   7
   8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   9         parameter [7:0] INIT = 0;
  10         assign OUT = INIT[{IN2, IN1, IN0}];
  11 endmodule
  12
  13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  14         parameter [15:0] INIT = 0;
  15         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  16 endmodule
  17
  18 module GP_ABUF(input wire IN, output wire OUT);
  19
  20         assign OUT = IN;
  21
  22         //cannot simulate mixed signal IP
  23
  24 endmodule
  25
  26 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  27
  28         parameter BANDWIDTH = "HIGH";
  29         parameter VIN_ATTEN = 1;
  30         parameter VIN_ISRC_EN = 0;
  31         parameter HYSTERESIS = 0;
  32
  33         initial OUT = 0;
  34
  35         //cannot simulate mixed signal IP
  36
  37 endmodule
  38
  39 module GP_BANDGAP(output reg OK);
  40         parameter AUTO_PWRDN = 1;
  41         parameter CHOPPER_EN = 1;
  42         parameter OUT_DELAY = 100;
  43
  44         //cannot simulate mixed signal IP
  45
  46 endmodule
  47
  48 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  49
  50         parameter RESET_MODE    = "RISING";
  51
  52         parameter COUNT_TO              = 8'h1;
  53         parameter CLKIN_DIVIDE  = 1;
  54
  55         //more complex hard IP blocks are not supported for simulation yet
  56
  57         reg[7:0] count = COUNT_TO;
  58
  59         //Combinatorially output whenever we wrap low
  60         always @(*) begin
  61                 OUT <= (count == 8'h0);
  62         end
  63
  64         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  65         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  66         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  67         always @(posedge CLK) begin
  68
  69                 count           <= count - 1'd1;
  70
  71                 if(count == 0)
  72                         count   <= COUNT_TO;
  73
  74                 /*
  75                 if((RESET_MODE == "RISING") && RST)
  76                         count   <= 0;
  77                 if((RESET_MODE == "FALLING") && !RST)
  78                         count   <= 0;
  79                 if((RESET_MODE == "BOTH") && RST)
  80                         count   <= 0;
  81                 */
  82         end
  83
  84 endmodule
  85
  86 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  87
  88         parameter RESET_MODE    = "RISING";
  89
  90         parameter COUNT_TO              = 14'h1;
  91         parameter CLKIN_DIVIDE  = 1;
  92
  93         //more complex hard IP blocks are not supported for simulation yet
  94
  95 endmodule
  96
  97 module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
  98                      input UP, input KEEP);
  99
 100         parameter RESET_MODE    = "RISING";
 101         parameter RESET_VALUE   = "ZERO";
 102
 103         parameter COUNT_TO              = 8'h1;
 104         parameter CLKIN_DIVIDE  = 1;
 105
 106         //more complex hard IP blocks are not supported for simulation yet
 107
 108 endmodule
 109
 110 module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 111                       input UP, input KEEP);
 112
 113         parameter RESET_MODE    = "RISING";
 114         parameter RESET_VALUE   = "ZERO";
 115
 116         parameter COUNT_TO              = 14'h1;
 117         parameter CLKIN_DIVIDE  = 1;
 118
 119         //more complex hard IP blocks are not supported for simulation yet
 120
 121 endmodule
 122
 123 module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
 124
 125         initial VOUT = 0;
 126
 127         //analog hard IP is not supported for simulation
 128
 129 endmodule
 130
 131 module GP_DELAY(input IN, output reg OUT);
 132
 133         parameter DELAY_STEPS = 1;
 134         parameter GLITCH_FILTER = 0;
 135
 136         initial OUT = 0;
 137
 138         generate
 139
 140                 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
 141                 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
 142                 always @(*) begin
 143                         case(DELAY_STEPS)
 144                                 1: #166 OUT = IN;
 145                                 2: #318 OUT = IN;
 146                                 2: #471 OUT = IN;
 147                                 3: #622 OUT = IN;
 148                                 default: begin
 149                                         $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
 150                                         $finish;
 151                                 end
 152                         endcase
 153                 end
 154
 155         endgenerate
 156
 157 endmodule
 158
 159 module GP_DFF(input D, CLK, output reg Q);
 160         parameter [0:0] INIT = 1'bx;
 161         initial Q = INIT;
 162         always @(posedge CLK) begin
 163                 Q <= D;
 164         end
 165 endmodule
 166
 167 module GP_DFFI(input D, CLK, output reg nQ);
 168         parameter [0:0] INIT = 1'bx;
 169         initial nQ = INIT;
 170         always @(posedge CLK) begin
 171                 nQ <= ~D;
 172         end
 173 endmodule
 174
 175 module GP_DFFR(input D, CLK, nRST, output reg Q);
 176         parameter [0:0] INIT = 1'bx;
 177         initial Q = INIT;
 178         always @(posedge CLK, negedge nRST) begin
 179                 if (!nRST)
 180                         Q <= 1'b0;
 181                 else
 182                         Q <= D;
 183         end
 184 endmodule
 185
 186 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
 187         parameter [0:0] INIT = 1'bx;
 188         initial nQ = INIT;
 189         always @(posedge CLK, negedge nRST) begin
 190                 if (!nRST)
 191                         nQ <= 1'b1;
 192                 else
 193                         nQ <= ~D;
 194         end
 195 endmodule
 196
 197 module GP_DFFS(input D, CLK, nSET, output reg Q);
 198         parameter [0:0] INIT = 1'bx;
 199         initial Q = INIT;
 200         always @(posedge CLK, negedge nSET) begin
 201                 if (!nSET)
 202                         Q <= 1'b1;
 203                 else
 204                         Q <= D;
 205         end
 206 endmodule
 207
 208 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
 209         parameter [0:0] INIT = 1'bx;
 210         initial nQ = INIT;
 211         always @(posedge CLK, negedge nSET) begin
 212                 if (!nSET)
 213                         nQ <= 1'b0;
 214                 else
 215                         nQ <= ~D;
 216         end
 217 endmodule
 218
 219 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 220         parameter [0:0] INIT = 1'bx;
 221         parameter [0:0] SRMODE = 1'bx;
 222         initial Q = INIT;
 223         always @(posedge CLK, negedge nSR) begin
 224                 if (!nSR)
 225                         Q <= SRMODE;
 226                 else
 227                         Q <= D;
 228         end
 229 endmodule
 230
 231 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
 232         parameter [0:0] INIT = 1'bx;
 233         parameter [0:0] SRMODE = 1'bx;
 234         initial nQ = INIT;
 235         always @(posedge CLK, negedge nSR) begin
 236                 if (!nSR)
 237                         nQ <= ~SRMODE;
 238                 else
 239                         nQ <= ~D;
 240         end
 241 endmodule
 242
 243 module GP_DLATCH(input D, input nCLK, output reg Q);
 244         parameter [0:0] INIT = 1'bx;
 245         initial Q = INIT;
 246         always @(*) begin
 247                 if(!nCLK)
 248                         Q <= D;
 249         end
 250 endmodule
 251
 252 module GP_DLATCHI(input D, input nCLK, output reg Q);
 253         parameter [0:0] INIT = 1'bx;
 254         initial Q = INIT;
 255         always @(*) begin
 256                 if(!nCLK)
 257                         Q <= ~D;
 258         end
 259 endmodule
 260
 261 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
 262         parameter [0:0] INIT = 1'bx;
 263         initial Q = INIT;
 264         always @(*) begin
 265                 if(!nRST)
 266                         Q <= 1'b0;
 267                 else if(!nCLK)
 268                         Q <= D;
 269         end
 270 endmodule
 271
 272 module GP_DLATCHRI(input D, input nCLK, input nRST, output reg Q);
 273         parameter [0:0] INIT = 1'bx;
 274         initial Q = INIT;
 275         always @(*) begin
 276                 if(!nRST)
 277                         Q <= 1'b1;
 278                 else if(!nCLK)
 279                         Q <= ~D;
 280         end
 281 endmodule
 282
 283 module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
 284         parameter [0:0] INIT = 1'bx;
 285         initial Q = INIT;
 286         always @(*) begin
 287                 if(!nSET)
 288                         Q <= 1'b1;
 289                 else if(!nCLK)
 290                         Q <= D;
 291         end
 292 endmodule
 293
 294 module GP_DLATCHSI(input D, input nCLK, input nSET, output reg Q);
 295         parameter [0:0] INIT = 1'bx;
 296         initial Q = INIT;
 297         always @(*) begin
 298                 if(!nSET)
 299                         Q <= 1'b0;
 300                 else if(!nCLK)
 301                         Q <= ~D;
 302         end
 303 endmodule
 304
 305 module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
 306         parameter [0:0] INIT = 1'bx;
 307         parameter[0:0] SRMODE = 1'bx;
 308         initial Q = INIT;
 309         always @(*) begin
 310                 if(!nSR)
 311                         Q <= SRMODE;
 312                 else if(!nCLK)
 313                         Q <= D;
 314         end
 315 endmodule
 316
 317 module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg Q);
 318         parameter [0:0] INIT = 1'bx;
 319         parameter[0:0] SRMODE = 1'bx;
 320         initial Q = INIT;
 321         always @(*) begin
 322                 if(!nSR)
 323                         Q <= ~SRMODE;
 324                 else if(!nCLK)
 325                         Q <= ~D;
 326         end
 327 endmodule
 328
 329 module GP_EDGEDET(input IN, output reg OUT);
 330
 331         parameter EDGE_DIRECTION = "RISING";
 332         parameter DELAY_STEPS = 1;
 333         parameter GLITCH_FILTER = 0;
 334
 335         //not implemented for simulation
 336
 337 endmodule
 338
 339 module GP_IBUF(input IN, output OUT);
 340         assign OUT = IN;
 341 endmodule
 342
 343 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
 344         assign OUT = IO;
 345         assign IO = OE ? IN : 1'bz;
 346 endmodule
 347
 348 module GP_INV(input IN, output OUT);
 349         assign OUT = ~IN;
 350 endmodule
 351
 352 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 353
 354         parameter PWRDN_EN = 0;
 355         parameter AUTO_PWRDN = 0;
 356         parameter OUT_DIV = 1;
 357
 358         initial CLKOUT = 0;
 359
 360         //auto powerdown not implemented for simulation
 361         //output dividers not implemented for simulation
 362
 363         always begin
 364                 if(PWRDN)
 365                         CLKOUT = 0;
 366                 else begin
 367                         //half period of 1730 Hz
 368                         #289017;
 369                         CLKOUT = ~CLKOUT;
 370                 end
 371         end
 372
 373 endmodule
 374
 375 module GP_OBUF(input IN, output OUT);
 376         assign OUT = IN;
 377 endmodule
 378
 379 module GP_OBUFT(input IN, input OE, output OUT);
 380         assign OUT = OE ? IN : 1'bz;
 381 endmodule
 382
 383 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
 384
 385         parameter GAIN = 1;
 386         parameter INPUT_MODE = "SINGLE";
 387
 388         initial VOUT = 0;
 389
 390         //cannot simulate mixed signal IP
 391
 392 endmodule
 393
 394 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 395         initial OUT = 0;
 396         parameter PATTERN_DATA = 16'h0;
 397         parameter PATTERN_LEN = 5'd16;
 398
 399         reg[3:0] count = 0;
 400         always @(posedge CLK) begin
 401                 if(!nRST)
 402                         OUT <= PATTERN_DATA[0];
 403
 404                 else begin
 405                         count <= count + 1;
 406                         OUT <= PATTERN_DATA[count];
 407
 408                         if( (count + 1) == PATTERN_LEN)
 409                                 count <= 0;
 410                 end
 411         end
 412
 413 endmodule
 414
 415 module GP_POR(output reg RST_DONE);
 416         parameter POR_TIME = 500;
 417
 418         initial begin
 419                 RST_DONE = 0;
 420
 421                 if(POR_TIME == 4)
 422                         #4000;
 423                 else if(POR_TIME == 500)
 424                         #500000;
 425                 else begin
 426                         $display("ERROR: bad POR_TIME for GP_POR cell");
 427                         $finish;
 428                 end
 429
 430                 RST_DONE = 1;
 431
 432         end
 433
 434 endmodule
 435
 436 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 437
 438         parameter PWRDN_EN = 0;
 439         parameter AUTO_PWRDN = 0;
 440         parameter HARDIP_DIV = 1;
 441         parameter FABRIC_DIV = 1;
 442         parameter OSC_FREQ = "25k";
 443
 444         initial CLKOUT_HARDIP = 0;
 445         initial CLKOUT_FABRIC = 0;
 446
 447         //output dividers not implemented for simulation
 448         //auto powerdown not implemented for simulation
 449
 450         always begin
 451                 if(PWRDN) begin
 452                         CLKOUT_HARDIP = 0;
 453                         CLKOUT_FABRIC = 0;
 454                 end
 455                 else begin
 456
 457                         if(OSC_FREQ == "25k") begin
 458                                 //half period of 25 kHz
 459                                 #20000;
 460                         end
 461
 462                         else begin
 463                                 //half period of 2 MHz
 464                                 #250;
 465                         end
 466
 467                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 468                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 469                 end
 470         end
 471
 472 endmodule
 473
 474 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
 475
 476         parameter PWRDN_EN = 0;
 477         parameter AUTO_PWRDN = 0;
 478         parameter HARDIP_DIV = 1;
 479         parameter FABRIC_DIV = 1;
 480
 481         initial CLKOUT_HARDIP = 0;
 482         initial CLKOUT_FABRIC = 0;
 483
 484         //output dividers not implemented for simulation
 485         //auto powerdown not implemented for simulation
 486
 487         always begin
 488                 if(PWRDN) begin
 489                         CLKOUT_HARDIP = 0;
 490                         CLKOUT_FABRIC = 0;
 491                 end
 492                 else begin
 493                         //half period of 27 MHz
 494                         #18.518;
 495                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
 496                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 497                 end
 498         end
 499
 500 endmodule
 501
 502 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 503
 504         parameter OUTA_TAP = 1;
 505         parameter OUTA_INVERT = 0;
 506         parameter OUTB_TAP = 1;
 507
 508         reg[15:0] shreg = 0;
 509
 510         always @(posedge CLK, negedge nRST) begin
 511
 512                 if(!nRST)
 513                         shreg = 0;
 514
 515                 else
 516                         shreg <= {shreg[14:0], IN};
 517
 518         end
 519
 520         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
 521         assign OUTB = shreg[OUTB_TAP - 1];
 522
 523 endmodule
 524
 525 //keep constraint needed to prevent optimization since we have no outputs
 526 (* keep *)
 527 module GP_SYSRESET(input RST);
 528         parameter RESET_MODE = "EDGE";
 529         parameter EDGE_SPEED = 4;
 530
 531         //cannot simulate whole system reset
 532
 533 endmodule
 534
 535 module GP_VDD(output OUT);
 536        assign OUT = 1;
 537 endmodule
 538
 539 module GP_VREF(input VIN, output reg VOUT);
 540         parameter VIN_DIV = 1;
 541         parameter VREF = 0;
 542         //cannot simulate mixed signal IP
 543 endmodule
 544
 545 module GP_VSS(output OUT);
 546        assign OUT = 0;
 547 endmodule