techlibs/greenpak4/cells_sim.v

   1 module GP_2LUT(input IN0, IN1, output OUT);
   2         parameter [3:0] INIT = 0;
   3         assign OUT = INIT[{IN1, IN0}];
   4 endmodule
   5
   6 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   7         parameter [7:0] INIT = 0;
   8         assign OUT = INIT[{IN2, IN1, IN0}];
   9 endmodule
  10
  11 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  12         parameter [15:0] INIT = 0;
  13         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  14 endmodule
  15
  16 module GP_ABUF(input wire IN, output wire OUT);
  17
  18         assign OUT = IN;
  19
  20         //cannot simulate mixed signal IP
  21
  22 endmodule
  23
  24 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  25
  26         parameter BANDWIDTH = "HIGH";
  27         parameter VIN_ATTEN = 1;
  28         parameter VIN_ISRC_EN = 0;
  29         parameter HYSTERESIS = 0;
  30
  31         initial OUT = 0;
  32
  33         //cannot simulate mixed signal IP
  34
  35 endmodule
  36
  37 module GP_BANDGAP(output reg OK, output reg VOUT);
  38         parameter AUTO_PWRDN = 1;
  39         parameter CHOPPER_EN = 1;
  40         parameter OUT_DELAY = 100;
  41
  42         //cannot simulate mixed signal IP
  43
  44 endmodule
  45
  46 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  47
  48         parameter RESET_MODE    = "RISING";
  49
  50         parameter COUNT_TO              = 8'h1;
  51         parameter CLKIN_DIVIDE  = 1;
  52
  53         //more complex hard IP blocks are not supported for simulation yet
  54
  55         reg[7:0] count = COUNT_TO;
  56
  57         //Combinatorially output whenever we wrap low
  58         always @(*) begin
  59                 OUT <= (count == 8'h0);
  60         end
  61
  62         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  63         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  64         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  65         always @(posedge CLK) begin
  66
  67                 count           <= count - 1'd1;
  68
  69                 if(count == 0)
  70                         count   <= COUNT_MAX;
  71
  72                 /*
  73                 if((RESET_MODE == "RISING") && RST)
  74                         count   <= 0;
  75                 if((RESET_MODE == "FALLING") && !RST)
  76                         count   <= 0;
  77                 if((RESET_MODE == "BOTH") && RST)
  78                         count   <= 0;
  79                 */
  80         end
  81
  82 endmodule
  83
  84 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  85
  86         parameter RESET_MODE    = "RISING";
  87
  88         parameter COUNT_TO              = 14'h1;
  89         parameter CLKIN_DIVIDE  = 1;
  90
  91         //more complex hard IP blocks are not supported for simulation yet
  92
  93 endmodule
  94
  95 module GP_DFF(input D, CLK, output reg Q);
  96         parameter [0:0] INIT = 1'bx;
  97         initial Q = INIT;
  98         always @(posedge CLK) begin
  99                 Q <= D;
 100         end
 101 endmodule
 102
 103 module GP_DFFR(input D, CLK, nRST, output reg Q);
 104         parameter [0:0] INIT = 1'bx;
 105         initial Q = INIT;
 106         always @(posedge CLK, negedge nRST) begin
 107                 if (!nRST)
 108                         Q <= 1'b0;
 109                 else
 110                         Q <= D;
 111         end
 112 endmodule
 113
 114 module GP_DFFS(input D, CLK, nSET, output reg Q);
 115         parameter [0:0] INIT = 1'bx;
 116         initial Q = INIT;
 117         always @(posedge CLK, negedge nSET) begin
 118                 if (!nSET)
 119                         Q <= 1'b1;
 120                 else
 121                         Q <= D;
 122         end
 123 endmodule
 124
 125 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 126         parameter [0:0] INIT = 1'bx;
 127         parameter [0:0] SRMODE = 1'bx;
 128         initial Q = INIT;
 129         always @(posedge CLK, negedge nSR) begin
 130                 if (!nSR)
 131                         Q <= SRMODE;
 132                 else
 133                         Q <= D;
 134         end
 135 endmodule
 136
 137 module GP_IBUF(input IN, output OUT);
 138         assign OUT = IN;
 139 endmodule
 140
 141 module GP_IOBUF(input IN, input DIR, output OUT, inout IO);
 142         assign IN = IO;
 143         assign DIR = OE ? OUT : 1'bz;
 144 endmodule
 145
 146 module GP_INV(input IN, output OUT);
 147         assign OUT = ~IN;
 148 endmodule
 149
 150 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 151
 152         parameter PWRDN_EN = 0;
 153         parameter AUTO_PWRDN = 0;
 154         parameter OUT_DIV = 1;
 155
 156         initial CLKOUT = 0;
 157
 158         //auto powerdown not implemented for simulation
 159         //output dividers not implemented for simulation
 160
 161         always begin
 162                 if(PWRDN)
 163                         CLKOUT = 0;
 164                 else begin
 165                         //half period of 1730 Hz
 166                         #289017;
 167                         CLKOUT = ~CLKOUT;
 168                 end
 169         end
 170
 171 endmodule
 172
 173 module GP_OBUF(input IN, output OUT);
 174         assign OUT = IN;
 175 endmodule
 176
 177 module GP_OBUFT(input IN, input OE, output OUT);
 178         assign OUT = OE ? IN : 1'bz;
 179 endmodule
 180
 181 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
 182
 183         parameter GAIN = 1;
 184         parameter INPUT_MODE = "SINGLE";
 185
 186         initial VOUT = 0;
 187
 188         //cannot simulate mixed signal IP
 189
 190 endmodule
 191
 192 module GP_POR(output reg RST_DONE);
 193         parameter POR_TIME = 500;
 194
 195         initial begin
 196                 RST_DONE = 0;
 197
 198                 if(POR_TIME == 4)
 199                         #4000;
 200                 else if(POR_TIME == 500)
 201                         #500000;
 202                 else begin
 203                         $display("ERROR: bad POR_TIME for GP_POR cell");
 204                         $finish;
 205                 end
 206
 207                 RST_DONE = 1;
 208
 209         end
 210
 211 endmodule
 212
 213 module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 214
 215         parameter PWRDN_EN = 0;
 216         parameter AUTO_PWRDN = 0;
 217         parameter PRE_DIV = 1;
 218         parameter FABRIC_DIV = 1;
 219         parameter OSC_FREQ = "25k";
 220
 221         initial CLKOUT_PREDIV = 0;
 222         initial CLKOUT_FABRIC = 0;
 223
 224         //output dividers not implemented for simulation
 225         //auto powerdown not implemented for simulation
 226
 227         always begin
 228                 if(PWRDN) begin
 229                         CLKOUT_PREDIV = 0;
 230                         CLKOUT_FABRIC = 0;
 231                 end
 232                 else begin
 233
 234                         if(OSC_FREQ == "25k") begin
 235                                 //half period of 25 kHz
 236                                 #20000;
 237                         end
 238
 239                         else begin
 240                                 //half period of 2 MHz
 241                                 #250;
 242                         end
 243
 244                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 245                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 246                 end
 247         end
 248
 249 endmodule
 250
 251 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 252
 253         parameter PWRDN_EN = 0;
 254         parameter AUTO_PWRDN = 0;
 255         parameter PRE_DIV = 1;
 256         parameter FABRIC_DIV = 1;
 257
 258         initial CLKOUT_PREDIV = 0;
 259         initial CLKOUT_FABRIC = 0;
 260
 261         //output dividers not implemented for simulation
 262         //auto powerdown not implemented for simulation
 263
 264         always begin
 265                 if(PWRDN) begin
 266                         CLKOUT_PREDIV = 0;
 267                         CLKOUT_FABRIC = 0;
 268                 end
 269                 else begin
 270                         //half period of 27 MHz
 271                         #18.518;
 272                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 273                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 274                 end
 275         end
 276
 277 endmodule
 278
 279 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 280
 281         parameter OUTA_DELAY = 1;
 282         parameter OUTA_INVERT = 0;
 283         parameter OUTB_DELAY = 1;
 284
 285         reg[15:0] shreg = 0;
 286
 287         always @(posedge clk, negedge nRST) begin
 288
 289                 if(!nRST)
 290                         shreg = 0;
 291
 292                 else
 293                         shreg <= {shreg[14:0], IN};
 294
 295         end
 296
 297         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1];
 298         assign OUTB = shreg[OUTB_DELAY - 1];
 299
 300 endmodule
 301
 302 //keep constraint needed to prevent optimization since we have no outputs
 303 (* keep *)
 304 module GP_SYSRESET(input RST);
 305         parameter RESET_MODE = "RISING";
 306
 307         //cannot simulate whole system reset
 308
 309 endmodule
 310
 311 module GP_VDD(output OUT);
 312        assign OUT = 1;
 313 endmodule
 314
 315 module GP_VREF(input VIN, output reg VOUT);
 316         parameter VIN_DIV = 1;
 317         parameter VREF = 0;
 318         //cannot simulate mixed signal IP
 319 endmodule
 320
 321 module GP_VSS(output OUT);
 322        assign OUT = 0;
 323 endmodule