3 module GP_2LUT(input IN0, IN1, output OUT);
4 parameter [3:0] INIT = 0;
5 assign OUT = INIT[{IN1, IN0}];
8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
9 parameter [7:0] INIT = 0;
10 assign OUT = INIT[{IN2, IN1, IN0}];
13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
14 parameter [15:0] INIT = 0;
15 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
18 module GP_ABUF(input wire IN, output wire OUT);
22 //must be 1, 5, 20, 50
23 //values >1 only available with Vdd > 2.7V
24 parameter BANDWIDTH_KHZ = 1;
26 //cannot simulate mixed signal IP
30 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
32 parameter BANDWIDTH = "HIGH";
33 parameter VIN_ATTEN = 1;
34 parameter VIN_ISRC_EN = 0;
35 parameter HYSTERESIS = 0;
39 //cannot simulate mixed signal IP
43 module GP_BANDGAP(output reg OK);
44 parameter AUTO_PWRDN = 1;
45 parameter CHOPPER_EN = 1;
46 parameter OUT_DELAY = 100;
48 //cannot simulate mixed signal IP
52 module GP_CLKBUF(input wire IN, output wire OUT);
56 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
58 parameter RESET_MODE = "RISING";
60 parameter COUNT_TO = 8'h1;
61 parameter CLKIN_DIVIDE = 1;
63 //more complex hard IP blocks are not supported for simulation yet
65 reg[7:0] count = COUNT_TO;
67 //Combinatorially output whenever we wrap low
69 OUT <= (count == 8'h0);
72 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
73 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
74 //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
75 always @(posedge CLK) begin
77 count <= count - 1'd1;
83 if((RESET_MODE == "RISING") && RST)
85 if((RESET_MODE == "FALLING") && !RST)
87 if((RESET_MODE == "BOTH") && RST)
94 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
96 parameter RESET_MODE = "RISING";
98 parameter COUNT_TO = 14'h1;
99 parameter CLKIN_DIVIDE = 1;
101 //more complex hard IP blocks are not supported for simulation yet
105 module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
106 input UP, input KEEP);
108 parameter RESET_MODE = "RISING";
109 parameter RESET_VALUE = "ZERO";
111 parameter COUNT_TO = 8'h1;
112 parameter CLKIN_DIVIDE = 1;
114 //more complex hard IP blocks are not supported for simulation yet
118 module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
119 input UP, input KEEP);
121 parameter RESET_MODE = "RISING";
122 parameter RESET_VALUE = "ZERO";
124 parameter COUNT_TO = 14'h1;
125 parameter CLKIN_DIVIDE = 1;
127 //more complex hard IP blocks are not supported for simulation yet
131 module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
135 //analog hard IP is not supported for simulation
139 module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
140 parameter PWRDN_SYNC = 1'b0;
141 parameter CLK_EDGE = "RISING";
142 parameter GREATER_OR_EQUAL = 1'b0;
144 //TODO implement power-down mode
149 wire clk_minv = (CLK_EDGE == "RISING") ? CLK : ~CLK;
150 always @(posedge clk_minv) begin
152 GREATER <= (INP >= INN);
154 GREATER <= (INP > INN);
156 EQUAL <= (INP == INN);
161 module GP_DCMPREF(output reg[7:0]OUT);
162 parameter[7:0] REF_VAL = 8'h00;
163 initial OUT = REF_VAL;
166 module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
194 module GP_DELAY(input IN, output reg OUT);
196 parameter DELAY_STEPS = 1;
197 parameter GLITCH_FILTER = 0;
203 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
204 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
212 $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
222 module GP_DFF(input D, CLK, output reg Q);
223 parameter [0:0] INIT = 1'bx;
225 always @(posedge CLK) begin
230 module GP_DFFI(input D, CLK, output reg nQ);
231 parameter [0:0] INIT = 1'bx;
233 always @(posedge CLK) begin
238 module GP_DFFR(input D, CLK, nRST, output reg Q);
239 parameter [0:0] INIT = 1'bx;
241 always @(posedge CLK, negedge nRST) begin
249 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
250 parameter [0:0] INIT = 1'bx;
252 always @(posedge CLK, negedge nRST) begin
260 module GP_DFFS(input D, CLK, nSET, output reg Q);
261 parameter [0:0] INIT = 1'bx;
263 always @(posedge CLK, negedge nSET) begin
271 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
272 parameter [0:0] INIT = 1'bx;
274 always @(posedge CLK, negedge nSET) begin
282 module GP_DFFSR(input D, CLK, nSR, output reg Q);
283 parameter [0:0] INIT = 1'bx;
284 parameter [0:0] SRMODE = 1'bx;
286 always @(posedge CLK, negedge nSR) begin
294 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
295 parameter [0:0] INIT = 1'bx;
296 parameter [0:0] SRMODE = 1'bx;
298 always @(posedge CLK, negedge nSR) begin
306 module GP_DLATCH(input D, input nCLK, output reg Q);
307 parameter [0:0] INIT = 1'bx;
315 module GP_DLATCHI(input D, input nCLK, output reg nQ);
316 parameter [0:0] INIT = 1'bx;
324 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
325 parameter [0:0] INIT = 1'bx;
335 module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
336 parameter [0:0] INIT = 1'bx;
346 module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
347 parameter [0:0] INIT = 1'bx;
357 module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
358 parameter [0:0] INIT = 1'bx;
368 module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
369 parameter [0:0] INIT = 1'bx;
370 parameter[0:0] SRMODE = 1'bx;
380 module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
381 parameter [0:0] INIT = 1'bx;
382 parameter[0:0] SRMODE = 1'bx;
392 module GP_EDGEDET(input IN, output reg OUT);
394 parameter EDGE_DIRECTION = "RISING";
395 parameter DELAY_STEPS = 1;
396 parameter GLITCH_FILTER = 0;
398 //not implemented for simulation
402 module GP_IBUF(input IN, output OUT);
406 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
408 assign IO = OE ? IN : 1'bz;
411 module GP_INV(input IN, output OUT);
415 module GP_LFOSC(input PWRDN, output reg CLKOUT);
417 parameter PWRDN_EN = 0;
418 parameter AUTO_PWRDN = 0;
419 parameter OUT_DIV = 1;
423 //auto powerdown not implemented for simulation
424 //output dividers not implemented for simulation
430 //half period of 1730 Hz
438 module GP_OBUF(input IN, output OUT);
442 module GP_OBUFT(input IN, input OE, output OUT);
443 assign OUT = OE ? IN : 1'bz;
446 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
449 parameter INPUT_MODE = "SINGLE";
453 //cannot simulate mixed signal IP
457 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
459 parameter PATTERN_DATA = 16'h0;
460 parameter PATTERN_LEN = 5'd16;
463 always @(posedge CLK) begin
465 OUT <= PATTERN_DATA[0];
469 OUT <= PATTERN_DATA[count];
471 if( (count + 1) == PATTERN_LEN)
478 module GP_PWRDET(output reg VDD_LOW);
482 module GP_POR(output reg RST_DONE);
483 parameter POR_TIME = 500;
490 else if(POR_TIME == 500)
493 $display("ERROR: bad POR_TIME for GP_POR cell");
503 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
505 parameter PWRDN_EN = 0;
506 parameter AUTO_PWRDN = 0;
507 parameter HARDIP_DIV = 1;
508 parameter FABRIC_DIV = 1;
509 parameter OSC_FREQ = "25k";
511 initial CLKOUT_HARDIP = 0;
512 initial CLKOUT_FABRIC = 0;
514 //output dividers not implemented for simulation
515 //auto powerdown not implemented for simulation
524 if(OSC_FREQ == "25k") begin
525 //half period of 25 kHz
530 //half period of 2 MHz
534 CLKOUT_HARDIP = ~CLKOUT_HARDIP;
535 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
541 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
543 parameter PWRDN_EN = 0;
544 parameter AUTO_PWRDN = 0;
545 parameter HARDIP_DIV = 1;
546 parameter FABRIC_DIV = 1;
548 initial CLKOUT_HARDIP = 0;
549 initial CLKOUT_FABRIC = 0;
551 //output dividers not implemented for simulation
552 //auto powerdown not implemented for simulation
560 //half period of 27 MHz
562 CLKOUT_HARDIP = ~CLKOUT_HARDIP;
563 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
569 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
571 parameter OUTA_TAP = 1;
572 parameter OUTA_INVERT = 0;
573 parameter OUTB_TAP = 1;
577 always @(posedge CLK, negedge nRST) begin
583 shreg <= {shreg[14:0], IN};
587 assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
588 assign OUTB = shreg[OUTB_TAP - 1];
599 output reg[7:0] RXD_HIGH,
600 output reg[7:0] RXD_LOW);
603 initial DOUT_HIGH = 0;
604 initial DOUT_LOW = 0;
606 parameter ADC_BUFFER = 0; //set true to use SPI data as ADC buffer... TODO
607 parameter DATA_WIDTH = 8; //byte or word width
608 parameter SPI_CPHA = 0; //SPI clock phase
609 parameter SPI_CPOL = 0; //SPI clock polarity
610 parameter DIRECTION = "INPUT"; //SPI data direction (either input to chip or output to host)
611 //parallel output to fabric not yet implemented
613 //TODO: write sim model
614 //TODO: SPI SDIO control... can we use ADC output while SPI is input??
619 //keep constraint needed to prevent optimization since we have no outputs
621 module GP_SYSRESET(input RST);
622 parameter RESET_MODE = "EDGE";
623 parameter EDGE_SPEED = 4;
625 //cannot simulate whole system reset
629 module GP_VDD(output OUT);
633 module GP_VREF(input VIN, output reg VOUT);
634 parameter VIN_DIV = 1;
636 //cannot simulate mixed signal IP
639 module GP_VSS(output OUT);