1 module GP_2LUT(input IN0, IN1, output OUT);
2 parameter [3:0] INIT = 0;
3 assign OUT = INIT[{IN1, IN0}];
6 module GP_3LUT(input IN0, IN1, IN2, output OUT);
7 parameter [7:0] INIT = 0;
8 assign OUT = INIT[{IN2, IN1, IN0}];
11 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
12 parameter [15:0] INIT = 0;
13 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
16 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
18 parameter BANDWIDTH = "HIGH";
19 parameter VIN_ATTEN = 1;
20 parameter VIN_ISRC_EN = 0;
21 parameter HYSTERESIS = 0;
25 //cannot simulate mixed signal IP
29 module GP_BANDGAP(output reg OK, output reg VOUT);
30 parameter AUTO_PWRDN = 1;
31 parameter CHOPPER_EN = 1;
32 parameter OUT_DELAY = 100;
34 //cannot simulate mixed signal IP
38 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
40 parameter RESET_MODE = "RISING";
42 parameter COUNT_TO = 8'h1;
43 parameter CLKIN_DIVIDE = 1;
45 //more complex hard IP blocks are not supported for simulation yet
47 reg[7:0] count = COUNT_TO;
49 //Combinatorially output whenever we wrap low
51 OUT <= (count == 8'h0);
54 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
55 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
56 //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
57 always @(posedge CLK) begin
59 count <= count - 1'd1;
65 if((RESET_MODE == "RISING") && RST)
67 if((RESET_MODE == "FALLING") && !RST)
69 if((RESET_MODE == "BOTH") && RST)
76 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
78 parameter RESET_MODE = "RISING";
80 parameter COUNT_TO = 14'h1;
81 parameter CLKIN_DIVIDE = 1;
83 //more complex hard IP blocks are not supported for simulation yet
87 module GP_DFF(input D, CLK, output reg Q);
88 parameter [0:0] INIT = 1'bx;
90 always @(posedge CLK) begin
95 module GP_DFFR(input D, CLK, nRST, output reg Q);
96 parameter [0:0] INIT = 1'bx;
98 always @(posedge CLK, negedge nRST) begin
106 module GP_DFFS(input D, CLK, nSET, output reg Q);
107 parameter [0:0] INIT = 1'bx;
109 always @(posedge CLK, negedge nSET) begin
117 module GP_DFFSR(input D, CLK, nSR, output reg Q);
118 parameter [0:0] INIT = 1'bx;
119 parameter [0:0] SRMODE = 1'bx;
121 always @(posedge CLK, negedge nSR) begin
129 module GP_INV(input IN, output OUT);
133 module GP_LFOSC(input PWRDN, output reg CLKOUT);
135 parameter PWRDN_EN = 0;
136 parameter AUTO_PWRDN = 0;
137 parameter OUT_DIV = 1;
141 //auto powerdown not implemented for simulation
142 //output dividers not implemented for simulation
148 //half period of 1730 Hz
156 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
159 parameter INPUT_MODE = "SINGLE";
163 //cannot simulate mixed signal IP
167 module GP_POR(output reg RST_DONE);
168 parameter POR_TIME = 500;
175 else if(POR_TIME == 500)
178 $display("ERROR: bad POR_TIME for GP_POR cell");
188 module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
190 parameter PWRDN_EN = 0;
191 parameter AUTO_PWRDN = 0;
192 parameter PRE_DIV = 1;
193 parameter FABRIC_DIV = 1;
194 parameter OSC_FREQ = "25k";
196 initial CLKOUT_PREDIV = 0;
197 initial CLKOUT_FABRIC = 0;
199 //output dividers not implemented for simulation
200 //auto powerdown not implemented for simulation
209 if(OSC_FREQ == "25k") begin
210 //half period of 25 kHz
215 //half period of 2 MHz
219 CLKOUT_PREDIV = ~CLKOUT_PREDIV;
220 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
226 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
228 parameter PWRDN_EN = 0;
229 parameter AUTO_PWRDN = 0;
230 parameter PRE_DIV = 1;
231 parameter FABRIC_DIV = 1;
233 initial CLKOUT_PREDIV = 0;
234 initial CLKOUT_FABRIC = 0;
236 //output dividers not implemented for simulation
237 //auto powerdown not implemented for simulation
245 //half period of 27 MHz
247 CLKOUT_PREDIV = ~CLKOUT_PREDIV;
248 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
254 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
256 parameter OUTA_DELAY = 1;
257 parameter OUTA_INVERT = 0;
258 parameter OUTB_DELAY = 1;
262 always @(posedge clk, negedge nRST) begin
268 shreg <= {shreg[14:0], IN};
272 assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1];
273 assign OUTB = shreg[OUTB_DELAY - 1];
277 //keep constraint needed to prevent optimization since we have no outputs
279 module GP_SYSRESET(input RST);
280 parameter RESET_MODE = "RISING";
282 //cannot simulate whole system reset
286 module GP_VDD(output OUT);
290 module GP_VREF(input VIN, output reg VOUT);
291 parameter VIN_DIV = 1;
293 //cannot simulate mixed signal IP
296 module GP_VSS(output OUT);