3 module GP_2LUT(input IN0, IN1, output OUT);
4 parameter [3:0] INIT = 0;
5 assign OUT = INIT[{IN1, IN0}];
8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
9 parameter [7:0] INIT = 0;
10 assign OUT = INIT[{IN2, IN1, IN0}];
13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
14 parameter [15:0] INIT = 0;
15 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
18 module GP_ABUF(input wire IN, output wire OUT);
22 //cannot simulate mixed signal IP
26 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
28 parameter BANDWIDTH = "HIGH";
29 parameter VIN_ATTEN = 1;
30 parameter VIN_ISRC_EN = 0;
31 parameter HYSTERESIS = 0;
35 //cannot simulate mixed signal IP
39 module GP_BANDGAP(output reg OK, output reg VOUT);
40 parameter AUTO_PWRDN = 1;
41 parameter CHOPPER_EN = 1;
42 parameter OUT_DELAY = 100;
44 //cannot simulate mixed signal IP
48 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
50 parameter RESET_MODE = "RISING";
52 parameter COUNT_TO = 8'h1;
53 parameter CLKIN_DIVIDE = 1;
55 //more complex hard IP blocks are not supported for simulation yet
57 reg[7:0] count = COUNT_TO;
59 //Combinatorially output whenever we wrap low
61 OUT <= (count == 8'h0);
64 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
65 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
66 //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
67 always @(posedge CLK) begin
69 count <= count - 1'd1;
75 if((RESET_MODE == "RISING") && RST)
77 if((RESET_MODE == "FALLING") && !RST)
79 if((RESET_MODE == "BOTH") && RST)
86 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
88 parameter RESET_MODE = "RISING";
90 parameter COUNT_TO = 14'h1;
91 parameter CLKIN_DIVIDE = 1;
93 //more complex hard IP blocks are not supported for simulation yet
97 module GP_DELAY(input IN, output reg OUT);
99 parameter DELAY_STEPS = 1;
101 //TODO: additional delay/glitch filter mode
107 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
108 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
116 $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
126 module GP_DFF(input D, CLK, output reg Q);
127 parameter [0:0] INIT = 1'bx;
129 always @(posedge CLK) begin
134 module GP_DFFR(input D, CLK, nRST, output reg Q);
135 parameter [0:0] INIT = 1'bx;
137 always @(posedge CLK, negedge nRST) begin
145 module GP_DFFS(input D, CLK, nSET, output reg Q);
146 parameter [0:0] INIT = 1'bx;
148 always @(posedge CLK, negedge nSET) begin
156 module GP_DFFSR(input D, CLK, nSR, output reg Q);
157 parameter [0:0] INIT = 1'bx;
158 parameter [0:0] SRMODE = 1'bx;
160 always @(posedge CLK, negedge nSR) begin
168 module GP_IBUF(input IN, output OUT);
172 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
174 assign IO = OE ? IN : 1'bz;
177 module GP_INV(input IN, output OUT);
181 module GP_LFOSC(input PWRDN, output reg CLKOUT);
183 parameter PWRDN_EN = 0;
184 parameter AUTO_PWRDN = 0;
185 parameter OUT_DIV = 1;
189 //auto powerdown not implemented for simulation
190 //output dividers not implemented for simulation
196 //half period of 1730 Hz
204 module GP_OBUF(input IN, output OUT);
208 module GP_OBUFT(input IN, input OE, output OUT);
209 assign OUT = OE ? IN : 1'bz;
212 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
215 parameter INPUT_MODE = "SINGLE";
219 //cannot simulate mixed signal IP
223 module GP_POR(output reg RST_DONE);
224 parameter POR_TIME = 500;
231 else if(POR_TIME == 500)
234 $display("ERROR: bad POR_TIME for GP_POR cell");
244 module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
246 parameter PWRDN_EN = 0;
247 parameter AUTO_PWRDN = 0;
248 parameter PRE_DIV = 1;
249 parameter FABRIC_DIV = 1;
250 parameter OSC_FREQ = "25k";
252 initial CLKOUT_PREDIV = 0;
253 initial CLKOUT_FABRIC = 0;
255 //output dividers not implemented for simulation
256 //auto powerdown not implemented for simulation
265 if(OSC_FREQ == "25k") begin
266 //half period of 25 kHz
271 //half period of 2 MHz
275 CLKOUT_PREDIV = ~CLKOUT_PREDIV;
276 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
282 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
284 parameter PWRDN_EN = 0;
285 parameter AUTO_PWRDN = 0;
286 parameter PRE_DIV = 1;
287 parameter FABRIC_DIV = 1;
289 initial CLKOUT_PREDIV = 0;
290 initial CLKOUT_FABRIC = 0;
292 //output dividers not implemented for simulation
293 //auto powerdown not implemented for simulation
301 //half period of 27 MHz
303 CLKOUT_PREDIV = ~CLKOUT_PREDIV;
304 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
310 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
312 parameter OUTA_TAP = 1;
313 parameter OUTA_INVERT = 0;
314 parameter OUTB_TAP = 1;
318 always @(posedge CLK, negedge nRST) begin
324 shreg <= {shreg[14:0], IN};
328 assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
329 assign OUTB = shreg[OUTB_TAP - 1];
333 //keep constraint needed to prevent optimization since we have no outputs
335 module GP_SYSRESET(input RST);
336 parameter RESET_MODE = "RISING";
338 //cannot simulate whole system reset
342 module GP_VDD(output OUT);
346 module GP_VREF(input VIN, output reg VOUT);
347 parameter VIN_DIV = 1;
349 //cannot simulate mixed signal IP
352 module GP_VSS(output OUT);