techlibs/greenpak4/cells_sim.v

   1 `timescale 1ns/1ps
   2
   3 module GP_2LUT(input IN0, IN1, output OUT);
   4         parameter [3:0] INIT = 0;
   5         assign OUT = INIT[{IN1, IN0}];
   6 endmodule
   7
   8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   9         parameter [7:0] INIT = 0;
  10         assign OUT = INIT[{IN2, IN1, IN0}];
  11 endmodule
  12
  13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  14         parameter [15:0] INIT = 0;
  15         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  16 endmodule
  17
  18 module GP_ABUF(input wire IN, output wire OUT);
  19
  20         assign OUT = IN;
  21
  22         //cannot simulate mixed signal IP
  23
  24 endmodule
  25
  26 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  27
  28         parameter BANDWIDTH = "HIGH";
  29         parameter VIN_ATTEN = 1;
  30         parameter VIN_ISRC_EN = 0;
  31         parameter HYSTERESIS = 0;
  32
  33         initial OUT = 0;
  34
  35         //cannot simulate mixed signal IP
  36
  37 endmodule
  38
  39 module GP_BANDGAP(output reg OK, output reg VOUT);
  40         parameter AUTO_PWRDN = 1;
  41         parameter CHOPPER_EN = 1;
  42         parameter OUT_DELAY = 100;
  43
  44         //cannot simulate mixed signal IP
  45
  46 endmodule
  47
  48 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  49
  50         parameter RESET_MODE    = "RISING";
  51
  52         parameter COUNT_TO              = 8'h1;
  53         parameter CLKIN_DIVIDE  = 1;
  54
  55         //more complex hard IP blocks are not supported for simulation yet
  56
  57         reg[7:0] count = COUNT_TO;
  58
  59         //Combinatorially output whenever we wrap low
  60         always @(*) begin
  61                 OUT <= (count == 8'h0);
  62         end
  63
  64         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  65         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  66         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  67         always @(posedge CLK) begin
  68
  69                 count           <= count - 1'd1;
  70
  71                 if(count == 0)
  72                         count   <= COUNT_TO;
  73
  74                 /*
  75                 if((RESET_MODE == "RISING") && RST)
  76                         count   <= 0;
  77                 if((RESET_MODE == "FALLING") && !RST)
  78                         count   <= 0;
  79                 if((RESET_MODE == "BOTH") && RST)
  80                         count   <= 0;
  81                 */
  82         end
  83
  84 endmodule
  85
  86 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  87
  88         parameter RESET_MODE    = "RISING";
  89
  90         parameter COUNT_TO              = 14'h1;
  91         parameter CLKIN_DIVIDE  = 1;
  92
  93         //more complex hard IP blocks are not supported for simulation yet
  94
  95 endmodule
  96
  97 module GP_DELAY(input IN, output reg OUT);
  98
  99         parameter DELAY_STEPS = 1;
 100
 101         //TODO: additional delay/glitch filter mode
 102
 103         initial OUT = 0;
 104
 105         generate
 106
 107                 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
 108                 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
 109                 always @(*) begin
 110                         case(DELAY_STEPS)
 111                                 1: #166 OUT = IN;
 112                                 2: #318 OUT = IN;
 113                                 2: #471 OUT = IN;
 114                                 3: #622 OUT = IN;
 115                                 default: begin
 116                                         $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
 117                                         $finish;
 118                                 end
 119                         endcase
 120                 end
 121
 122         endgenerate
 123
 124 endmodule
 125
 126 module GP_DFF(input D, CLK, output reg Q);
 127         parameter [0:0] INIT = 1'bx;
 128         initial Q = INIT;
 129         always @(posedge CLK) begin
 130                 Q <= D;
 131         end
 132 endmodule
 133
 134 module GP_DFFR(input D, CLK, nRST, output reg Q);
 135         parameter [0:0] INIT = 1'bx;
 136         initial Q = INIT;
 137         always @(posedge CLK, negedge nRST) begin
 138                 if (!nRST)
 139                         Q <= 1'b0;
 140                 else
 141                         Q <= D;
 142         end
 143 endmodule
 144
 145 module GP_DFFS(input D, CLK, nSET, output reg Q);
 146         parameter [0:0] INIT = 1'bx;
 147         initial Q = INIT;
 148         always @(posedge CLK, negedge nSET) begin
 149                 if (!nSET)
 150                         Q <= 1'b1;
 151                 else
 152                         Q <= D;
 153         end
 154 endmodule
 155
 156 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 157         parameter [0:0] INIT = 1'bx;
 158         parameter [0:0] SRMODE = 1'bx;
 159         initial Q = INIT;
 160         always @(posedge CLK, negedge nSR) begin
 161                 if (!nSR)
 162                         Q <= SRMODE;
 163                 else
 164                         Q <= D;
 165         end
 166 endmodule
 167
 168 module GP_IBUF(input IN, output OUT);
 169         assign OUT = IN;
 170 endmodule
 171
 172 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
 173         assign OUT = IO;
 174         assign IO = OE ? IN : 1'bz;
 175 endmodule
 176
 177 module GP_INV(input IN, output OUT);
 178         assign OUT = ~IN;
 179 endmodule
 180
 181 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 182
 183         parameter PWRDN_EN = 0;
 184         parameter AUTO_PWRDN = 0;
 185         parameter OUT_DIV = 1;
 186
 187         initial CLKOUT = 0;
 188
 189         //auto powerdown not implemented for simulation
 190         //output dividers not implemented for simulation
 191
 192         always begin
 193                 if(PWRDN)
 194                         CLKOUT = 0;
 195                 else begin
 196                         //half period of 1730 Hz
 197                         #289017;
 198                         CLKOUT = ~CLKOUT;
 199                 end
 200         end
 201
 202 endmodule
 203
 204 module GP_OBUF(input IN, output OUT);
 205         assign OUT = IN;
 206 endmodule
 207
 208 module GP_OBUFT(input IN, input OE, output OUT);
 209         assign OUT = OE ? IN : 1'bz;
 210 endmodule
 211
 212 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
 213
 214         parameter GAIN = 1;
 215         parameter INPUT_MODE = "SINGLE";
 216
 217         initial VOUT = 0;
 218
 219         //cannot simulate mixed signal IP
 220
 221 endmodule
 222
 223 module GP_POR(output reg RST_DONE);
 224         parameter POR_TIME = 500;
 225
 226         initial begin
 227                 RST_DONE = 0;
 228
 229                 if(POR_TIME == 4)
 230                         #4000;
 231                 else if(POR_TIME == 500)
 232                         #500000;
 233                 else begin
 234                         $display("ERROR: bad POR_TIME for GP_POR cell");
 235                         $finish;
 236                 end
 237
 238                 RST_DONE = 1;
 239
 240         end
 241
 242 endmodule
 243
 244 module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 245
 246         parameter PWRDN_EN = 0;
 247         parameter AUTO_PWRDN = 0;
 248         parameter PRE_DIV = 1;
 249         parameter FABRIC_DIV = 1;
 250         parameter OSC_FREQ = "25k";
 251
 252         initial CLKOUT_PREDIV = 0;
 253         initial CLKOUT_FABRIC = 0;
 254
 255         //output dividers not implemented for simulation
 256         //auto powerdown not implemented for simulation
 257
 258         always begin
 259                 if(PWRDN) begin
 260                         CLKOUT_PREDIV = 0;
 261                         CLKOUT_FABRIC = 0;
 262                 end
 263                 else begin
 264
 265                         if(OSC_FREQ == "25k") begin
 266                                 //half period of 25 kHz
 267                                 #20000;
 268                         end
 269
 270                         else begin
 271                                 //half period of 2 MHz
 272                                 #250;
 273                         end
 274
 275                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 276                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 277                 end
 278         end
 279
 280 endmodule
 281
 282 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 283
 284         parameter PWRDN_EN = 0;
 285         parameter AUTO_PWRDN = 0;
 286         parameter PRE_DIV = 1;
 287         parameter FABRIC_DIV = 1;
 288
 289         initial CLKOUT_PREDIV = 0;
 290         initial CLKOUT_FABRIC = 0;
 291
 292         //output dividers not implemented for simulation
 293         //auto powerdown not implemented for simulation
 294
 295         always begin
 296                 if(PWRDN) begin
 297                         CLKOUT_PREDIV = 0;
 298                         CLKOUT_FABRIC = 0;
 299                 end
 300                 else begin
 301                         //half period of 27 MHz
 302                         #18.518;
 303                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 304                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 305                 end
 306         end
 307
 308 endmodule
 309
 310 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 311
 312         parameter OUTA_TAP = 1;
 313         parameter OUTA_INVERT = 0;
 314         parameter OUTB_TAP = 1;
 315
 316         reg[15:0] shreg = 0;
 317
 318         always @(posedge CLK, negedge nRST) begin
 319
 320                 if(!nRST)
 321                         shreg = 0;
 322
 323                 else
 324                         shreg <= {shreg[14:0], IN};
 325
 326         end
 327
 328         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
 329         assign OUTB = shreg[OUTB_TAP - 1];
 330
 331 endmodule
 332
 333 //keep constraint needed to prevent optimization since we have no outputs
 334 (* keep *)
 335 module GP_SYSRESET(input RST);
 336         parameter RESET_MODE = "RISING";
 337
 338         //cannot simulate whole system reset
 339
 340 endmodule
 341
 342 module GP_VDD(output OUT);
 343        assign OUT = 1;
 344 endmodule
 345
 346 module GP_VREF(input VIN, output reg VOUT);
 347         parameter VIN_DIV = 1;
 348         parameter VREF = 0;
 349         //cannot simulate mixed signal IP
 350 endmodule
 351
 352 module GP_VSS(output OUT);
 353        assign OUT = 0;
 354 endmodule