techlibs/greenpak4/cells_sim.v

   1 `timescale 1ns/1ps;
   2
   3 module GP_2LUT(input IN0, IN1, output OUT);
   4         parameter [3:0] INIT = 0;
   5         assign OUT = INIT[{IN1, IN0}];
   6 endmodule
   7
   8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   9         parameter [7:0] INIT = 0;
  10         assign OUT = INIT[{IN2, IN1, IN0}];
  11 endmodule
  12
  13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  14         parameter [15:0] INIT = 0;
  15         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  16 endmodule
  17
  18 module GP_ABUF(input wire IN, output wire OUT);
  19
  20         assign OUT = IN;
  21
  22         //cannot simulate mixed signal IP
  23
  24 endmodule
  25
  26 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  27
  28         parameter BANDWIDTH = "HIGH";
  29         parameter VIN_ATTEN = 1;
  30         parameter VIN_ISRC_EN = 0;
  31         parameter HYSTERESIS = 0;
  32
  33         initial OUT = 0;
  34
  35         //cannot simulate mixed signal IP
  36
  37 endmodule
  38
  39 module GP_BANDGAP(output reg OK, output reg VOUT);
  40         parameter AUTO_PWRDN = 1;
  41         parameter CHOPPER_EN = 1;
  42         parameter OUT_DELAY = 100;
  43
  44         //cannot simulate mixed signal IP
  45
  46 endmodule
  47
  48 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  49
  50         parameter RESET_MODE    = "RISING";
  51
  52         parameter COUNT_TO              = 8'h1;
  53         parameter CLKIN_DIVIDE  = 1;
  54
  55         //more complex hard IP blocks are not supported for simulation yet
  56
  57         reg[7:0] count = COUNT_TO;
  58
  59         //Combinatorially output whenever we wrap low
  60         always @(*) begin
  61                 OUT <= (count == 8'h0);
  62         end
  63
  64         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  65         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  66         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  67         always @(posedge CLK) begin
  68
  69                 count           <= count - 1'd1;
  70
  71                 if(count == 0)
  72                         count   <= COUNT_TO;
  73
  74                 /*
  75                 if((RESET_MODE == "RISING") && RST)
  76                         count   <= 0;
  77                 if((RESET_MODE == "FALLING") && !RST)
  78                         count   <= 0;
  79                 if((RESET_MODE == "BOTH") && RST)
  80                         count   <= 0;
  81                 */
  82         end
  83
  84 endmodule
  85
  86 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  87
  88         parameter RESET_MODE    = "RISING";
  89
  90         parameter COUNT_TO              = 14'h1;
  91         parameter CLKIN_DIVIDE  = 1;
  92
  93         //more complex hard IP blocks are not supported for simulation yet
  94
  95 endmodule
  96
  97 module GP_DFF(input D, CLK, output reg Q);
  98         parameter [0:0] INIT = 1'bx;
  99         initial Q = INIT;
 100         always @(posedge CLK) begin
 101                 Q <= D;
 102         end
 103 endmodule
 104
 105 module GP_DFFR(input D, CLK, nRST, output reg Q);
 106         parameter [0:0] INIT = 1'bx;
 107         initial Q = INIT;
 108         always @(posedge CLK, negedge nRST) begin
 109                 if (!nRST)
 110                         Q <= 1'b0;
 111                 else
 112                         Q <= D;
 113         end
 114 endmodule
 115
 116 module GP_DFFS(input D, CLK, nSET, output reg Q);
 117         parameter [0:0] INIT = 1'bx;
 118         initial Q = INIT;
 119         always @(posedge CLK, negedge nSET) begin
 120                 if (!nSET)
 121                         Q <= 1'b1;
 122                 else
 123                         Q <= D;
 124         end
 125 endmodule
 126
 127 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 128         parameter [0:0] INIT = 1'bx;
 129         parameter [0:0] SRMODE = 1'bx;
 130         initial Q = INIT;
 131         always @(posedge CLK, negedge nSR) begin
 132                 if (!nSR)
 133                         Q <= SRMODE;
 134                 else
 135                         Q <= D;
 136         end
 137 endmodule
 138
 139 module GP_IBUF(input IN, output OUT);
 140         assign OUT = IN;
 141 endmodule
 142
 143 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
 144         assign OUT = IO;
 145         assign IO = OE ? IN : 1'bz;
 146 endmodule
 147
 148 module GP_INV(input IN, output OUT);
 149         assign OUT = ~IN;
 150 endmodule
 151
 152 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 153
 154         parameter PWRDN_EN = 0;
 155         parameter AUTO_PWRDN = 0;
 156         parameter OUT_DIV = 1;
 157
 158         initial CLKOUT = 0;
 159
 160         //auto powerdown not implemented for simulation
 161         //output dividers not implemented for simulation
 162
 163         always begin
 164                 if(PWRDN)
 165                         CLKOUT = 0;
 166                 else begin
 167                         //half period of 1730 Hz
 168                         #289017;
 169                         CLKOUT = ~CLKOUT;
 170                 end
 171         end
 172
 173 endmodule
 174
 175 module GP_OBUF(input IN, output OUT);
 176         assign OUT = IN;
 177 endmodule
 178
 179 module GP_OBUFT(input IN, input OE, output OUT);
 180         assign OUT = OE ? IN : 1'bz;
 181 endmodule
 182
 183 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
 184
 185         parameter GAIN = 1;
 186         parameter INPUT_MODE = "SINGLE";
 187
 188         initial VOUT = 0;
 189
 190         //cannot simulate mixed signal IP
 191
 192 endmodule
 193
 194 module GP_POR(output reg RST_DONE);
 195         parameter POR_TIME = 500;
 196
 197         initial begin
 198                 RST_DONE = 0;
 199
 200                 if(POR_TIME == 4)
 201                         #4000;
 202                 else if(POR_TIME == 500)
 203                         #500000;
 204                 else begin
 205                         $display("ERROR: bad POR_TIME for GP_POR cell");
 206                         $finish;
 207                 end
 208
 209                 RST_DONE = 1;
 210
 211         end
 212
 213 endmodule
 214
 215 module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 216
 217         parameter PWRDN_EN = 0;
 218         parameter AUTO_PWRDN = 0;
 219         parameter PRE_DIV = 1;
 220         parameter FABRIC_DIV = 1;
 221         parameter OSC_FREQ = "25k";
 222
 223         initial CLKOUT_PREDIV = 0;
 224         initial CLKOUT_FABRIC = 0;
 225
 226         //output dividers not implemented for simulation
 227         //auto powerdown not implemented for simulation
 228
 229         always begin
 230                 if(PWRDN) begin
 231                         CLKOUT_PREDIV = 0;
 232                         CLKOUT_FABRIC = 0;
 233                 end
 234                 else begin
 235
 236                         if(OSC_FREQ == "25k") begin
 237                                 //half period of 25 kHz
 238                                 #20000;
 239                         end
 240
 241                         else begin
 242                                 //half period of 2 MHz
 243                                 #250;
 244                         end
 245
 246                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 247                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 248                 end
 249         end
 250
 251 endmodule
 252
 253 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 254
 255         parameter PWRDN_EN = 0;
 256         parameter AUTO_PWRDN = 0;
 257         parameter PRE_DIV = 1;
 258         parameter FABRIC_DIV = 1;
 259
 260         initial CLKOUT_PREDIV = 0;
 261         initial CLKOUT_FABRIC = 0;
 262
 263         //output dividers not implemented for simulation
 264         //auto powerdown not implemented for simulation
 265
 266         always begin
 267                 if(PWRDN) begin
 268                         CLKOUT_PREDIV = 0;
 269                         CLKOUT_FABRIC = 0;
 270                 end
 271                 else begin
 272                         //half period of 27 MHz
 273                         #18.518;
 274                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 275                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 276                 end
 277         end
 278
 279 endmodule
 280
 281 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 282
 283         parameter OUTA_TAP = 1;
 284         parameter OUTA_INVERT = 0;
 285         parameter OUTB_TAP = 1;
 286
 287         reg[15:0] shreg = 0;
 288
 289         always @(posedge clk, negedge nRST) begin
 290
 291                 if(!nRST)
 292                         shreg = 0;
 293
 294                 else
 295                         shreg <= {shreg[14:0], IN};
 296
 297         end
 298
 299         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
 300         assign OUTB = shreg[OUTB_TAP - 1];
 301
 302 endmodule
 303
 304 //keep constraint needed to prevent optimization since we have no outputs
 305 (* keep *)
 306 module GP_SYSRESET(input RST);
 307         parameter RESET_MODE = "RISING";
 308
 309         //cannot simulate whole system reset
 310
 311 endmodule
 312
 313 module GP_VDD(output OUT);
 314        assign OUT = 1;
 315 endmodule
 316
 317 module GP_VREF(input VIN, output reg VOUT);
 318         parameter VIN_DIV = 1;
 319         parameter VREF = 0;
 320         //cannot simulate mixed signal IP
 321 endmodule
 322
 323 module GP_VSS(output OUT);
 324        assign OUT = 0;
 325 endmodule