3 module GP_2LUT(input IN0, IN1, output OUT);
4 parameter [3:0] INIT = 0;
5 assign OUT = INIT[{IN1, IN0}];
8 module GP_3LUT(input IN0, IN1, IN2, output OUT);
9 parameter [7:0] INIT = 0;
10 assign OUT = INIT[{IN2, IN1, IN0}];
13 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
14 parameter [15:0] INIT = 0;
15 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
18 module GP_ABUF(input wire IN, output wire OUT);
22 //cannot simulate mixed signal IP
26 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
28 parameter BANDWIDTH = "HIGH";
29 parameter VIN_ATTEN = 1;
30 parameter VIN_ISRC_EN = 0;
31 parameter HYSTERESIS = 0;
35 //cannot simulate mixed signal IP
39 module GP_BANDGAP(output reg OK, output reg VOUT);
40 parameter AUTO_PWRDN = 1;
41 parameter CHOPPER_EN = 1;
42 parameter OUT_DELAY = 100;
44 //cannot simulate mixed signal IP
48 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
50 parameter RESET_MODE = "RISING";
52 parameter COUNT_TO = 8'h1;
53 parameter CLKIN_DIVIDE = 1;
55 //more complex hard IP blocks are not supported for simulation yet
57 reg[7:0] count = COUNT_TO;
59 //Combinatorially output whenever we wrap low
61 OUT <= (count == 8'h0);
64 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
65 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
66 //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
67 always @(posedge CLK) begin
69 count <= count - 1'd1;
75 if((RESET_MODE == "RISING") && RST)
77 if((RESET_MODE == "FALLING") && !RST)
79 if((RESET_MODE == "BOTH") && RST)
86 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
88 parameter RESET_MODE = "RISING";
90 parameter COUNT_TO = 14'h1;
91 parameter CLKIN_DIVIDE = 1;
93 //more complex hard IP blocks are not supported for simulation yet
97 module GP_DFF(input D, CLK, output reg Q);
98 parameter [0:0] INIT = 1'bx;
100 always @(posedge CLK) begin
105 module GP_DFFR(input D, CLK, nRST, output reg Q);
106 parameter [0:0] INIT = 1'bx;
108 always @(posedge CLK, negedge nRST) begin
116 module GP_DFFS(input D, CLK, nSET, output reg Q);
117 parameter [0:0] INIT = 1'bx;
119 always @(posedge CLK, negedge nSET) begin
127 module GP_DFFSR(input D, CLK, nSR, output reg Q);
128 parameter [0:0] INIT = 1'bx;
129 parameter [0:0] SRMODE = 1'bx;
131 always @(posedge CLK, negedge nSR) begin
139 module GP_IBUF(input IN, output OUT);
143 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
145 assign IO = OE ? IN : 1'bz;
148 module GP_INV(input IN, output OUT);
152 module GP_LFOSC(input PWRDN, output reg CLKOUT);
154 parameter PWRDN_EN = 0;
155 parameter AUTO_PWRDN = 0;
156 parameter OUT_DIV = 1;
160 //auto powerdown not implemented for simulation
161 //output dividers not implemented for simulation
167 //half period of 1730 Hz
175 module GP_OBUF(input IN, output OUT);
179 module GP_OBUFT(input IN, input OE, output OUT);
180 assign OUT = OE ? IN : 1'bz;
183 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
186 parameter INPUT_MODE = "SINGLE";
190 //cannot simulate mixed signal IP
194 module GP_POR(output reg RST_DONE);
195 parameter POR_TIME = 500;
202 else if(POR_TIME == 500)
205 $display("ERROR: bad POR_TIME for GP_POR cell");
215 module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
217 parameter PWRDN_EN = 0;
218 parameter AUTO_PWRDN = 0;
219 parameter PRE_DIV = 1;
220 parameter FABRIC_DIV = 1;
221 parameter OSC_FREQ = "25k";
223 initial CLKOUT_PREDIV = 0;
224 initial CLKOUT_FABRIC = 0;
226 //output dividers not implemented for simulation
227 //auto powerdown not implemented for simulation
236 if(OSC_FREQ == "25k") begin
237 //half period of 25 kHz
242 //half period of 2 MHz
246 CLKOUT_PREDIV = ~CLKOUT_PREDIV;
247 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
253 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
255 parameter PWRDN_EN = 0;
256 parameter AUTO_PWRDN = 0;
257 parameter PRE_DIV = 1;
258 parameter FABRIC_DIV = 1;
260 initial CLKOUT_PREDIV = 0;
261 initial CLKOUT_FABRIC = 0;
263 //output dividers not implemented for simulation
264 //auto powerdown not implemented for simulation
272 //half period of 27 MHz
274 CLKOUT_PREDIV = ~CLKOUT_PREDIV;
275 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
281 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
283 parameter OUTA_TAP = 1;
284 parameter OUTA_INVERT = 0;
285 parameter OUTB_TAP = 1;
289 always @(posedge clk, negedge nRST) begin
295 shreg <= {shreg[14:0], IN};
299 assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
300 assign OUTB = shreg[OUTB_TAP - 1];
304 //keep constraint needed to prevent optimization since we have no outputs
306 module GP_SYSRESET(input RST);
307 parameter RESET_MODE = "RISING";
309 //cannot simulate whole system reset
313 module GP_VDD(output OUT);
317 module GP_VREF(input VIN, output reg VOUT);
318 parameter VIN_DIV = 1;
320 //cannot simulate mixed signal IP
323 module GP_VSS(output OUT);