f8593b9fb60cb83ae188175794686d2fd6893967
[yosys.git] / techlibs / greenpak4 / cells_sim.v
1 module GP_DFF(input D, CLK, nRSTZ, nSETZ, output reg Q);
2 parameter [0:0] INIT = 1'bx;
3 initial Q = INIT;
4 always @(posedge CLK, negedge nRSTZ, negedge nSETZ) begin
5 if (!nRSTZ)
6 Q <= 1'b0;
7 else if (!nSETZ)
8 Q <= 1'b1;
9 else
10 Q <= D;
11 end
12 endmodule
13
14 module GP_2LUT(input IN0, IN1, output OUT);
15 parameter [3:0] INIT = 0;
16 assign OUT = INIT[{IN1, IN0}];
17 endmodule
18
19 module GP_3LUT(input IN0, IN1, IN2, output OUT);
20 parameter [7:0] INIT = 0;
21 assign OUT = INIT[{IN2, IN1, IN0}];
22 endmodule
23
24 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
25 parameter [15:0] INIT = 0;
26 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
27 endmodule