techlibs/greenpak4/cells_sim.v

   1 module GP_DFF(input D, CLK, output reg Q);
   2         parameter [0:0] INIT = 1'bx;
   3         initial Q = INIT;
   4         always @(posedge CLK) begin
   5                 Q <= D;
   6         end
   7 endmodule
   8
   9 module GP_DFFS(input D, CLK, nSET, output reg Q);
  10         parameter [0:0] INIT = 1'bx;
  11         initial Q = INIT;
  12         always @(posedge CLK, negedge nSET) begin
  13                 if (!nSET)
  14                         Q <= 1'b1;
  15                 else
  16                         Q <= D;
  17         end
  18 endmodule
  19
  20 module GP_DFFR(input D, CLK, nRST, output reg Q);
  21         parameter [0:0] INIT = 1'bx;
  22         initial Q = INIT;
  23         always @(posedge CLK, negedge nRST) begin
  24                 if (!nRST)
  25                         Q <= 1'b0;
  26                 else
  27                         Q <= D;
  28         end
  29 endmodule
  30
  31 module GP_DFFSR(input D, CLK, nSR, output reg Q);
  32         parameter [0:0] INIT = 1'bx;
  33         parameter [0:0] SRMODE = 1'bx;
  34         initial Q = INIT;
  35         always @(posedge CLK, negedge nSR) begin
  36                 if (!nSR)
  37                         Q <= SRMODE;
  38                 else
  39                         Q <= D;
  40         end
  41 endmodule
  42
  43 module GP_INV(input IN, output OUT);
  44         assign OUT = ~IN;
  45 endmodule
  46
  47 module GP_2LUT(input IN0, IN1, output OUT);
  48         parameter [3:0] INIT = 0;
  49         assign OUT = INIT[{IN1, IN0}];
  50 endmodule
  51
  52 module GP_3LUT(input IN0, IN1, IN2, output OUT);
  53         parameter [7:0] INIT = 0;
  54         assign OUT = INIT[{IN2, IN1, IN0}];
  55 endmodule
  56
  57 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  58         parameter [15:0] INIT = 0;
  59         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  60 endmodule
  61
  62 module GP_VDD(output OUT);
  63        assign OUT = 1;
  64 endmodule
  65
  66 module GP_VSS(output OUT);
  67        assign OUT = 0;
  68 endmodule
  69
  70 module GP_LFOSC(input PWRDN, output reg CLKOUT);
  71
  72         parameter PWRDN_EN = 0;
  73         parameter AUTO_PWRDN = 0;
  74         parameter OUT_DIV = 1;
  75
  76         initial CLKOUT = 0;
  77
  78         always begin
  79                 if(PWRDN)
  80                         clkout = 0;
  81                 else begin
  82                         //half period of 1730 Hz
  83                         #289017;
  84                         clkout = ~clkout;
  85                 end
  86         end
  87
  88 endmodule
  89
  90 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  91
  92         parameter RESET_MODE    = "RISING";
  93
  94         parameter COUNT_TO              = 8'h1;
  95         parameter CLKIN_DIVIDE  = 1;
  96
  97         //more complex hard IP blocks are not supported for simulation yet
  98
  99         reg[7:0] count = COUNT_TO;
 100
 101         //Combinatorially output whenever we wrap low
 102         always @(*) begin
 103                 OUT <= (count == 8'h0);
 104         end
 105
 106         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
 107         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
 108         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
 109         always @(posedge CLK) begin
 110
 111                 count           <= count - 1'd1;
 112
 113                 if(count == 0)
 114                         count   <= COUNT_MAX;
 115
 116                 /*
 117                 if((RESET_MODE == "RISING") && RST)
 118                         count   <= 0;
 119                 if((RESET_MODE == "FALLING") && !RST)
 120                         count   <= 0;
 121                 if((RESET_MODE == "BOTH") && RST)
 122                         count   <= 0;
 123                 */
 124         end
 125
 126 endmodule
 127
 128 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 129
 130         parameter RESET_MODE    = "RISING";
 131
 132         parameter COUNT_TO              = 14'h1;
 133         parameter CLKIN_DIVIDE  = 1;
 134
 135         //more complex hard IP blocks are not supported for simulation yet
 136
 137 endmodule
 138
 139 //keep constraint needed to prevent optimization since we have no outputs
 140 (* keep *)
 141 module GP_SYSRESET(input RST);
 142         parameter RESET_MODE = "RISING";
 143
 144         //cannot simulate whole system reset
 145
 146 endmodule