techlibs/greenpak4/cells_sim.v

   1 module GP_DFF(input D, CLK, output reg Q);
   2         parameter [0:0] INIT = 1'bx;
   3         initial Q = INIT;
   4         always @(posedge CLK) begin
   5                 Q <= D;
   6         end
   7 endmodule
   8
   9 module GP_DFFS(input D, CLK, nSET, output reg Q);
  10         parameter [0:0] INIT = 1'bx;
  11         initial Q = INIT;
  12         always @(posedge CLK, negedge nSET) begin
  13                 if (!nSET)
  14                         Q <= 1'b1;
  15                 else
  16                         Q <= D;
  17         end
  18 endmodule
  19
  20 module GP_DFFR(input D, CLK, nRST, output reg Q);
  21         parameter [0:0] INIT = 1'bx;
  22         initial Q = INIT;
  23         always @(posedge CLK, negedge nRST) begin
  24                 if (!nRST)
  25                         Q <= 1'b0;
  26                 else
  27                         Q <= D;
  28         end
  29 endmodule
  30
  31 module GP_DFFSR(input D, CLK, nSR, output reg Q);
  32         parameter [0:0] INIT = 1'bx;
  33         parameter [0:0] SRMODE = 1'bx;
  34         initial Q = INIT;
  35         always @(posedge CLK, negedge nSR) begin
  36                 if (!nSR)
  37                         Q <= SRMODE;
  38                 else
  39                         Q <= D;
  40         end
  41 endmodule
  42
  43 module GP_2LUT(input IN0, IN1, output OUT);
  44         parameter [3:0] INIT = 0;
  45         assign OUT = INIT[{IN1, IN0}];
  46 endmodule
  47
  48 module GP_3LUT(input IN0, IN1, IN2, output OUT);
  49         parameter [7:0] INIT = 0;
  50         assign OUT = INIT[{IN2, IN1, IN0}];
  51 endmodule
  52
  53 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  54         parameter [15:0] INIT = 0;
  55         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  56 endmodule
  57
  58 module GP_VDD(output OUT);
  59        assign OUT = 1;
  60 endmodule
  61
  62 module GP_VSS(output OUT);
  63        assign OUT = 0;
  64 endmodule
  65
  66 module GP_LFOSC(input PWRDN, output reg CLKOUT);
  67
  68         parameter PWRDN_EN = 0;
  69         parameter AUTO_PWRDN = 0;
  70         parameter OUT_DIV = 1;
  71
  72         initial CLKOUT = 0;
  73
  74         always begin
  75                 if(PWRDN)
  76                         clkout = 0;
  77                 else begin
  78                         //half period of 1730 Hz
  79                         #289017;
  80                         clkout = ~clkout;
  81                 end
  82         end
  83
  84 endmodule
  85
  86 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  87
  88         parameter RESET_MODE    = "RISING";
  89
  90         parameter COUNT_TO              = 8'h1;
  91         parameter CLKIN_DIVIDE  = 1;
  92
  93         //more complex hard IP blocks are not supported for simulation yet
  94
  95 endmodule
  96
  97 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  98
  99         parameter RESET_MODE    = "RISING";
 100
 101         parameter COUNT_TO              = 14'h1;
 102         parameter CLKIN_DIVIDE  = 1;
 103
 104         //more complex hard IP blocks are not supported for simulation yet
 105
 106 endmodule