techlibs/greenpak4/cells_sim.v

   1 module GP_DFF(input D, CLK, output reg Q);
   2         parameter [0:0] INIT = 1'bx;
   3         initial Q = INIT;
   4         always @(posedge CLK) begin
   5                 Q <= D;
   6         end
   7 endmodule
   8
   9 module GP_DFFS(input D, CLK, nSET, output reg Q);
  10         parameter [0:0] INIT = 1'bx;
  11         initial Q = INIT;
  12         always @(posedge CLK, negedge nSET) begin
  13                 if (!nSET)
  14                         Q <= 1'b1;
  15                 else
  16                         Q <= D;
  17         end
  18 endmodule
  19
  20 module GP_DFFR(input D, CLK, nRST, output reg Q);
  21         parameter [0:0] INIT = 1'bx;
  22         initial Q = INIT;
  23         always @(posedge CLK, negedge nRST) begin
  24                 if (!nRST)
  25                         Q <= 1'b0;
  26                 else
  27                         Q <= D;
  28         end
  29 endmodule
  30
  31 module GP_DFFSR(input D, CLK, nSR, output reg Q);
  32         parameter [0:0] INIT = 1'bx;
  33         parameter [0:0] SRMODE = 1'bx;
  34         initial Q = INIT;
  35         always @(posedge CLK, negedge nSR) begin
  36                 if (!nSR)
  37                         Q <= SRMODE;
  38                 else
  39                         Q <= D;
  40         end
  41 endmodule
  42
  43 module GP_INV(input IN, output OUT);
  44         assign OUT = ~IN;
  45 endmodule
  46
  47 module GP_2LUT(input IN0, IN1, output OUT);
  48         parameter [3:0] INIT = 0;
  49         assign OUT = INIT[{IN1, IN0}];
  50 endmodule
  51
  52 module GP_3LUT(input IN0, IN1, IN2, output OUT);
  53         parameter [7:0] INIT = 0;
  54         assign OUT = INIT[{IN2, IN1, IN0}];
  55 endmodule
  56
  57 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  58         parameter [15:0] INIT = 0;
  59         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  60 endmodule
  61
  62 module GP_VDD(output OUT);
  63        assign OUT = 1;
  64 endmodule
  65
  66 module GP_VSS(output OUT);
  67        assign OUT = 0;
  68 endmodule
  69
  70 module GP_LFOSC(input PWRDN, output reg CLKOUT);
  71
  72         parameter PWRDN_EN = 0;
  73         parameter AUTO_PWRDN = 0;
  74         parameter OUT_DIV = 1;
  75
  76         initial CLKOUT = 0;
  77
  78         //auto powerdown not implemented for simulation
  79         //output dividers not implemented for simulation
  80
  81         always begin
  82                 if(PWRDN)
  83                         CLKOUT = 0;
  84                 else begin
  85                         //half period of 1730 Hz
  86                         #289017;
  87                         CLKOUT = ~CLKOUT;
  88                 end
  89         end
  90
  91 endmodule
  92
  93 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
  94
  95         parameter PWRDN_EN = 0;
  96         parameter AUTO_PWRDN = 0;
  97         parameter PRE_DIV = 1;
  98         parameter FABRIC_DIV = 1;
  99
 100         initial CLKOUT_PREDIV = 0;
 101         initial CLKOUT_FABRIC = 0;
 102
 103         //output dividers not implemented for simulation
 104         //auto powerdown not implemented for simulation
 105
 106         always begin
 107                 if(PWRDN) begin
 108                         CLKOUT_PREDIV = 0;
 109                         CLKOUT_FABRIC = 0;
 110                 end
 111                 else begin
 112                         //half period of 27 MHz
 113                         #18.518;
 114                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 115                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 116                 end
 117         end
 118
 119 endmodule
 120
 121 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
 122
 123         parameter RESET_MODE    = "RISING";
 124
 125         parameter COUNT_TO              = 8'h1;
 126         parameter CLKIN_DIVIDE  = 1;
 127
 128         //more complex hard IP blocks are not supported for simulation yet
 129
 130         reg[7:0] count = COUNT_TO;
 131
 132         //Combinatorially output whenever we wrap low
 133         always @(*) begin
 134                 OUT <= (count == 8'h0);
 135         end
 136
 137         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
 138         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
 139         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
 140         always @(posedge CLK) begin
 141
 142                 count           <= count - 1'd1;
 143
 144                 if(count == 0)
 145                         count   <= COUNT_MAX;
 146
 147                 /*
 148                 if((RESET_MODE == "RISING") && RST)
 149                         count   <= 0;
 150                 if((RESET_MODE == "FALLING") && !RST)
 151                         count   <= 0;
 152                 if((RESET_MODE == "BOTH") && RST)
 153                         count   <= 0;
 154                 */
 155         end
 156
 157 endmodule
 158
 159 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 160
 161         parameter RESET_MODE    = "RISING";
 162
 163         parameter COUNT_TO              = 14'h1;
 164         parameter CLKIN_DIVIDE  = 1;
 165
 166         //more complex hard IP blocks are not supported for simulation yet
 167
 168 endmodule
 169
 170 //keep constraint needed to prevent optimization since we have no outputs
 171 (* keep *)
 172 module GP_SYSRESET(input RST);
 173         parameter RESET_MODE = "RISING";
 174
 175         //cannot simulate whole system reset
 176
 177 endmodule
 178
 179 module GP_BANDGAP(output reg OK, output reg VOUT);
 180         parameter AUTO_PWRDN = 1;
 181         parameter CHOPPER_EN = 1;
 182         parameter OUT_DELAY = 100;
 183
 184         //cannot simulate mixed signal IP
 185
 186 endmodule
 187
 188
 189 module GP_POR(output reg RST_DONE);
 190         parameter POR_TIME = 500;
 191
 192         initial begin
 193                 RST_DONE = 0;
 194
 195                 if(POR_TIME == 4)
 196                         #4000;
 197                 else if(POR_TIME == 500)
 198                         #500000;
 199                 else begin
 200                         $display("ERROR: bad POR_TIME for GP_POR cell");
 201                         $finish;
 202                 end
 203
 204                 RST_DONE = 1;
 205
 206         end
 207
 208 endmodule