1 module GP_DFF(input D, CLK, output reg Q);
2 parameter [0:0] INIT = 1'bx;
4 always @(posedge CLK) begin
9 module GP_DFFS(input D, CLK, nSET, output reg Q);
10 parameter [0:0] INIT = 1'bx;
12 always @(posedge CLK, negedge nSET) begin
20 module GP_DFFR(input D, CLK, nRST, output reg Q);
21 parameter [0:0] INIT = 1'bx;
23 always @(posedge CLK, negedge nRST) begin
31 module GP_DFFSR(input D, CLK, nSR, output reg Q);
32 parameter [0:0] INIT = 1'bx;
33 parameter [0:0] SRMODE = 1'bx;
35 always @(posedge CLK, negedge nSR) begin
43 module GP_INV(input IN, output OUT);
47 module GP_2LUT(input IN0, IN1, output OUT);
48 parameter [3:0] INIT = 0;
49 assign OUT = INIT[{IN1, IN0}];
52 module GP_3LUT(input IN0, IN1, IN2, output OUT);
53 parameter [7:0] INIT = 0;
54 assign OUT = INIT[{IN2, IN1, IN0}];
57 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
58 parameter [15:0] INIT = 0;
59 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
62 module GP_VDD(output OUT);
66 module GP_VSS(output OUT);
70 module GP_LFOSC(input PWRDN, output reg CLKOUT);
72 parameter PWRDN_EN = 0;
73 parameter AUTO_PWRDN = 0;
74 parameter OUT_DIV = 1;
78 //auto powerdown not implemented for simulation
79 //output dividers not implemented for simulation
85 //half period of 1730 Hz
93 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
95 parameter PWRDN_EN = 0;
96 parameter AUTO_PWRDN = 0;
97 parameter PRE_DIV = 1;
98 parameter FABRIC_DIV = 1;
100 initial CLKOUT_PREDIV = 0;
101 initial CLKOUT_FABRIC = 0;
103 //output dividers not implemented for simulation
104 //auto powerdown not implemented for simulation
112 //half period of 27 MHz
114 CLKOUT_PREDIV = ~CLKOUT_PREDIV;
115 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
121 module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
123 parameter PWRDN_EN = 0;
124 parameter AUTO_PWRDN = 0;
125 parameter PRE_DIV = 1;
126 parameter FABRIC_DIV = 1;
127 parameter OSC_FREQ = "25k"
129 initial CLKOUT_PREDIV = 0;
130 initial CLKOUT_FABRIC = 0;
132 //output dividers not implemented for simulation
133 //auto powerdown not implemented for simulation
142 if(OSC_FREQ == "25k") begin
143 //half period of 25 kHz
148 //half period of 2 MHz
152 CLKOUT_PREDIV = ~CLKOUT_PREDIV;
153 CLKOUT_FABRIC = ~CLKOUT_FABRIC;
159 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
161 parameter RESET_MODE = "RISING";
163 parameter COUNT_TO = 8'h1;
164 parameter CLKIN_DIVIDE = 1;
166 //more complex hard IP blocks are not supported for simulation yet
168 reg[7:0] count = COUNT_TO;
170 //Combinatorially output whenever we wrap low
172 OUT <= (count == 8'h0);
175 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
176 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
177 //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
178 always @(posedge CLK) begin
180 count <= count - 1'd1;
186 if((RESET_MODE == "RISING") && RST)
188 if((RESET_MODE == "FALLING") && !RST)
190 if((RESET_MODE == "BOTH") && RST)
197 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
199 parameter RESET_MODE = "RISING";
201 parameter COUNT_TO = 14'h1;
202 parameter CLKIN_DIVIDE = 1;
204 //more complex hard IP blocks are not supported for simulation yet
208 //keep constraint needed to prevent optimization since we have no outputs
210 module GP_SYSRESET(input RST);
211 parameter RESET_MODE = "RISING";
213 //cannot simulate whole system reset
217 module GP_BANDGAP(output reg OK, output reg VOUT);
218 parameter AUTO_PWRDN = 1;
219 parameter CHOPPER_EN = 1;
220 parameter OUT_DELAY = 100;
222 //cannot simulate mixed signal IP
227 module GP_POR(output reg RST_DONE);
228 parameter POR_TIME = 500;
235 else if(POR_TIME == 500)
238 $display("ERROR: bad POR_TIME for GP_POR cell");