1 module GP_DFF(input D, CLK, output reg Q);
2 parameter [0:0] INIT = 1'bx;
4 always @(posedge CLK) begin
9 module GP_DFFS(input D, CLK, nSET, output reg Q);
10 parameter [0:0] INIT = 1'bx;
12 always @(posedge CLK, negedge nSET) begin
20 module GP_DFFR(input D, CLK, nRST, output reg Q);
21 parameter [0:0] INIT = 1'bx;
23 always @(posedge CLK, negedge nRST) begin
31 module GP_DFFSR(input D, CLK, nSR, output reg Q);
32 parameter [0:0] INIT = 1'bx;
33 parameter [0:0] SRMODE = 1'bx;
35 always @(posedge CLK, negedge nSR) begin
43 module GP_2LUT(input IN0, IN1, output OUT);
44 parameter [3:0] INIT = 0;
45 assign OUT = INIT[{IN1, IN0}];
48 module GP_3LUT(input IN0, IN1, IN2, output OUT);
49 parameter [7:0] INIT = 0;
50 assign OUT = INIT[{IN2, IN1, IN0}];
53 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
54 parameter [15:0] INIT = 0;
55 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
58 module GP_VDD(output OUT);
62 module GP_VSS(output OUT);
66 module GP_LFOSC(input PWRDN, output reg CLKOUT);
68 parameter PWRDN_EN = 0;
69 parameter AUTO_PWRDN = 0;
70 parameter OUT_DIV = 1;
78 //half period of 1730 Hz
86 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
88 parameter RESET_MODE = "RISING";
90 parameter COUNT_TO = 8'h1;
91 parameter CLKIN_DIVIDE = 1;
93 //more complex hard IP blocks are not supported for simulation yet
95 reg[7:0] count = COUNT_TO;
97 //Combinatorially output whenever we wrap low
99 OUT <= (count == 8'h0);
102 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
103 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
104 //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
105 always @(posedge CLK) begin
107 count <= count - 1'd1;
113 if((RESET_MODE == "RISING") && RST)
115 if((RESET_MODE == "FALLING") && !RST)
117 if((RESET_MODE == "BOTH") && RST)
124 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
126 parameter RESET_MODE = "RISING";
128 parameter COUNT_TO = 14'h1;
129 parameter CLKIN_DIVIDE = 1;
131 //more complex hard IP blocks are not supported for simulation yet
135 //keep constraint needed to prevent optimization since we have no outputs
137 module GP_SYSRESET(input RST);
138 parameter RESET_MODE = "RISING";
140 //cannot simulate whole system reset