techlibs/greenpak4/cells_sim.v

   1 module GP_DFF(input D, CLK, output reg Q);
   2         parameter [0:0] INIT = 1'bx;
   3         initial Q = INIT;
   4         always @(posedge CLK) begin
   5                 Q <= D;
   6         end
   7 endmodule
   8
   9 module GP_DFFS(input D, CLK, nSET, output reg Q);
  10         parameter [0:0] INIT = 1'bx;
  11         initial Q = INIT;
  12         always @(posedge CLK, negedge nSET) begin
  13                 if (!nSET)
  14                         Q <= 1'b1;
  15                 else
  16                         Q <= D;
  17         end
  18 endmodule
  19
  20 module GP_DFFR(input D, CLK, nRST, output reg Q);
  21         parameter [0:0] INIT = 1'bx;
  22         initial Q = INIT;
  23         always @(posedge CLK, negedge nRST) begin
  24                 if (!nRST)
  25                         Q <= 1'b0;
  26                 else
  27                         Q <= D;
  28         end
  29 endmodule
  30
  31 module GP_DFFSR(input D, CLK, nSR, output reg Q);
  32         parameter [0:0] INIT = 1'bx;
  33         parameter [0:0] SRMODE = 1'bx;
  34         initial Q = INIT;
  35         always @(posedge CLK, negedge nSR) begin
  36                 if (!nSR)
  37                         Q <= SRMODE;
  38                 else
  39                         Q <= D;
  40         end
  41 endmodule
  42
  43 module GP_INV(input IN, output OUT);
  44         assign OUT = ~IN;
  45 endmodule
  46
  47 module GP_2LUT(input IN0, IN1, output OUT);
  48         parameter [3:0] INIT = 0;
  49         assign OUT = INIT[{IN1, IN0}];
  50 endmodule
  51
  52 module GP_3LUT(input IN0, IN1, IN2, output OUT);
  53         parameter [7:0] INIT = 0;
  54         assign OUT = INIT[{IN2, IN1, IN0}];
  55 endmodule
  56
  57 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  58         parameter [15:0] INIT = 0;
  59         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  60 endmodule
  61
  62 module GP_VDD(output OUT);
  63        assign OUT = 1;
  64 endmodule
  65
  66 module GP_VSS(output OUT);
  67        assign OUT = 0;
  68 endmodule
  69
  70 module GP_LFOSC(input PWRDN, output reg CLKOUT);
  71
  72         parameter PWRDN_EN = 0;
  73         parameter AUTO_PWRDN = 0;
  74         parameter OUT_DIV = 1;
  75
  76         initial CLKOUT = 0;
  77
  78         //auto powerdown not implemented for simulation
  79         //output dividers not implemented for simulation
  80
  81         always begin
  82                 if(PWRDN)
  83                         CLKOUT = 0;
  84                 else begin
  85                         //half period of 1730 Hz
  86                         #289017;
  87                         CLKOUT = ~CLKOUT;
  88                 end
  89         end
  90
  91 endmodule
  92
  93 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
  94
  95         parameter PWRDN_EN = 0;
  96         parameter AUTO_PWRDN = 0;
  97         parameter PRE_DIV = 1;
  98         parameter FABRIC_DIV = 1;
  99
 100         initial CLKOUT_PREDIV = 0;
 101         initial CLKOUT_FABRIC = 0;
 102
 103         //output dividers not implemented for simulation
 104         //auto powerdown not implemented for simulation
 105
 106         always begin
 107                 if(PWRDN) begin
 108                         CLKOUT_PREDIV = 0;
 109                         CLKOUT_FABRIC = 0;
 110                 end
 111                 else begin
 112                         //half period of 27 MHz
 113                         #18.518;
 114                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 115                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 116                 end
 117         end
 118
 119 endmodule
 120
 121 module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 122
 123         parameter PWRDN_EN = 0;
 124         parameter AUTO_PWRDN = 0;
 125         parameter PRE_DIV = 1;
 126         parameter FABRIC_DIV = 1;
 127         parameter OSC_FREQ = "25k"
 128
 129         initial CLKOUT_PREDIV = 0;
 130         initial CLKOUT_FABRIC = 0;
 131
 132         //output dividers not implemented for simulation
 133         //auto powerdown not implemented for simulation
 134
 135         always begin
 136                 if(PWRDN) begin
 137                         CLKOUT_PREDIV = 0;
 138                         CLKOUT_FABRIC = 0;
 139                 end
 140                 else begin
 141
 142                         if(OSC_FREQ == "25k") begin
 143                                 //half period of 25 kHz
 144                                 #20000;
 145                         end
 146
 147                         else begin
 148                                 //half period of 2 MHz
 149                                 #250;
 150                         end
 151
 152                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 153                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 154                 end
 155         end
 156
 157 endmodule
 158
 159 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
 160
 161         parameter RESET_MODE    = "RISING";
 162
 163         parameter COUNT_TO              = 8'h1;
 164         parameter CLKIN_DIVIDE  = 1;
 165
 166         //more complex hard IP blocks are not supported for simulation yet
 167
 168         reg[7:0] count = COUNT_TO;
 169
 170         //Combinatorially output whenever we wrap low
 171         always @(*) begin
 172                 OUT <= (count == 8'h0);
 173         end
 174
 175         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
 176         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
 177         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
 178         always @(posedge CLK) begin
 179
 180                 count           <= count - 1'd1;
 181
 182                 if(count == 0)
 183                         count   <= COUNT_MAX;
 184
 185                 /*
 186                 if((RESET_MODE == "RISING") && RST)
 187                         count   <= 0;
 188                 if((RESET_MODE == "FALLING") && !RST)
 189                         count   <= 0;
 190                 if((RESET_MODE == "BOTH") && RST)
 191                         count   <= 0;
 192                 */
 193         end
 194
 195 endmodule
 196
 197 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 198
 199         parameter RESET_MODE    = "RISING";
 200
 201         parameter COUNT_TO              = 14'h1;
 202         parameter CLKIN_DIVIDE  = 1;
 203
 204         //more complex hard IP blocks are not supported for simulation yet
 205
 206 endmodule
 207
 208 //keep constraint needed to prevent optimization since we have no outputs
 209 (* keep *)
 210 module GP_SYSRESET(input RST);
 211         parameter RESET_MODE = "RISING";
 212
 213         //cannot simulate whole system reset
 214
 215 endmodule
 216
 217 module GP_BANDGAP(output reg OK, output reg VOUT);
 218         parameter AUTO_PWRDN = 1;
 219         parameter CHOPPER_EN = 1;
 220         parameter OUT_DELAY = 100;
 221
 222         //cannot simulate mixed signal IP
 223
 224 endmodule
 225
 226
 227 module GP_POR(output reg RST_DONE);
 228         parameter POR_TIME = 500;
 229
 230         initial begin
 231                 RST_DONE = 0;
 232
 233                 if(POR_TIME == 4)
 234                         #4000;
 235                 else if(POR_TIME == 500)
 236                         #500000;
 237                 else begin
 238                         $display("ERROR: bad POR_TIME for GP_POR cell");
 239                         $finish;
 240                 end
 241
 242                 RST_DONE = 1;
 243
 244         end
 245
 246 endmodule