techlibs/greenpak4/cells_sim.v

   1 module DFF(input D, CLK, nRSTZ, nSETZ, output reg Q);
   2         always @(posedge CLK, negedge nRSTZ, negedge nSETZ) begin
   3                 if (!nRSTZ)
   4                         Q <= 1'b0;
   5                 else if (!nSETZ)
   6                         Q <= 1'b1;
   7                 else
   8                         Q <= D;
   9         end
  10 endmodule
  11
  12 module LUT2(input IN0, IN1, output OUT);
  13         parameter [3:0] INIT = 0;
  14         assign OUT = INIT[{IN1, IN0}];
  15 endmodule
  16
  17 module LUT3(input IN0, IN1, IN2, output OUT);
  18         parameter [7:0] INIT = 0;
  19         assign OUT = INIT[{IN2, IN1, IN0}];
  20 endmodule
  21
  22 module LUT4(input IN0, IN1, IN2, IN3, output OUT);
  23         parameter [15:0] INIT = 0;
  24         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  25 endmodule