techlibs/greenpak4/cells_sim.v

   1 module GP_2LUT(input IN0, IN1, output OUT);
   2         parameter [3:0] INIT = 0;
   3         assign OUT = INIT[{IN1, IN0}];
   4 endmodule
   5
   6 module GP_3LUT(input IN0, IN1, IN2, output OUT);
   7         parameter [7:0] INIT = 0;
   8         assign OUT = INIT[{IN2, IN1, IN0}];
   9 endmodule
  10
  11 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  12         parameter [15:0] INIT = 0;
  13         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  14 endmodule
  15
  16 module GP_BANDGAP(output reg OK, output reg VOUT);
  17         parameter AUTO_PWRDN = 1;
  18         parameter CHOPPER_EN = 1;
  19         parameter OUT_DELAY = 100;
  20
  21         //cannot simulate mixed signal IP
  22
  23 endmodule
  24
  25 module GP_COUNT8(input CLK, input wire RST, output reg OUT);
  26
  27         parameter RESET_MODE    = "RISING";
  28
  29         parameter COUNT_TO              = 8'h1;
  30         parameter CLKIN_DIVIDE  = 1;
  31
  32         //more complex hard IP blocks are not supported for simulation yet
  33
  34         reg[7:0] count = COUNT_TO;
  35
  36         //Combinatorially output whenever we wrap low
  37         always @(*) begin
  38                 OUT <= (count == 8'h0);
  39         end
  40
  41         //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
  42         //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
  43         //Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
  44         always @(posedge CLK) begin
  45
  46                 count           <= count - 1'd1;
  47
  48                 if(count == 0)
  49                         count   <= COUNT_MAX;
  50
  51                 /*
  52                 if((RESET_MODE == "RISING") && RST)
  53                         count   <= 0;
  54                 if((RESET_MODE == "FALLING") && !RST)
  55                         count   <= 0;
  56                 if((RESET_MODE == "BOTH") && RST)
  57                         count   <= 0;
  58                 */
  59         end
  60
  61 endmodule
  62
  63 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
  64
  65         parameter RESET_MODE    = "RISING";
  66
  67         parameter COUNT_TO              = 14'h1;
  68         parameter CLKIN_DIVIDE  = 1;
  69
  70         //more complex hard IP blocks are not supported for simulation yet
  71
  72 endmodule
  73
  74 module GP_DFF(input D, CLK, output reg Q);
  75         parameter [0:0] INIT = 1'bx;
  76         initial Q = INIT;
  77         always @(posedge CLK) begin
  78                 Q <= D;
  79         end
  80 endmodule
  81
  82 module GP_DFFR(input D, CLK, nRST, output reg Q);
  83         parameter [0:0] INIT = 1'bx;
  84         initial Q = INIT;
  85         always @(posedge CLK, negedge nRST) begin
  86                 if (!nRST)
  87                         Q <= 1'b0;
  88                 else
  89                         Q <= D;
  90         end
  91 endmodule
  92
  93 module GP_DFFS(input D, CLK, nSET, output reg Q);
  94         parameter [0:0] INIT = 1'bx;
  95         initial Q = INIT;
  96         always @(posedge CLK, negedge nSET) begin
  97                 if (!nSET)
  98                         Q <= 1'b1;
  99                 else
 100                         Q <= D;
 101         end
 102 endmodule
 103
 104 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 105         parameter [0:0] INIT = 1'bx;
 106         parameter [0:0] SRMODE = 1'bx;
 107         initial Q = INIT;
 108         always @(posedge CLK, negedge nSR) begin
 109                 if (!nSR)
 110                         Q <= SRMODE;
 111                 else
 112                         Q <= D;
 113         end
 114 endmodule
 115
 116 module GP_INV(input IN, output OUT);
 117         assign OUT = ~IN;
 118 endmodule
 119
 120 module GP_LFOSC(input PWRDN, output reg CLKOUT);
 121
 122         parameter PWRDN_EN = 0;
 123         parameter AUTO_PWRDN = 0;
 124         parameter OUT_DIV = 1;
 125
 126         initial CLKOUT = 0;
 127
 128         //auto powerdown not implemented for simulation
 129         //output dividers not implemented for simulation
 130
 131         always begin
 132                 if(PWRDN)
 133                         CLKOUT = 0;
 134                 else begin
 135                         //half period of 1730 Hz
 136                         #289017;
 137                         CLKOUT = ~CLKOUT;
 138                 end
 139         end
 140
 141 endmodule
 142
 143 module GP_POR(output reg RST_DONE);
 144         parameter POR_TIME = 500;
 145
 146         initial begin
 147                 RST_DONE = 0;
 148
 149                 if(POR_TIME == 4)
 150                         #4000;
 151                 else if(POR_TIME == 500)
 152                         #500000;
 153                 else begin
 154                         $display("ERROR: bad POR_TIME for GP_POR cell");
 155                         $finish;
 156                 end
 157
 158                 RST_DONE = 1;
 159
 160         end
 161
 162 endmodule
 163
 164 module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 165
 166         parameter PWRDN_EN = 0;
 167         parameter AUTO_PWRDN = 0;
 168         parameter PRE_DIV = 1;
 169         parameter FABRIC_DIV = 1;
 170         parameter OSC_FREQ = "25k";
 171
 172         initial CLKOUT_PREDIV = 0;
 173         initial CLKOUT_FABRIC = 0;
 174
 175         //output dividers not implemented for simulation
 176         //auto powerdown not implemented for simulation
 177
 178         always begin
 179                 if(PWRDN) begin
 180                         CLKOUT_PREDIV = 0;
 181                         CLKOUT_FABRIC = 0;
 182                 end
 183                 else begin
 184
 185                         if(OSC_FREQ == "25k") begin
 186                                 //half period of 25 kHz
 187                                 #20000;
 188                         end
 189
 190                         else begin
 191                                 //half period of 2 MHz
 192                                 #250;
 193                         end
 194
 195                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 196                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 197                 end
 198         end
 199
 200 endmodule
 201
 202 module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC);
 203
 204         parameter PWRDN_EN = 0;
 205         parameter AUTO_PWRDN = 0;
 206         parameter PRE_DIV = 1;
 207         parameter FABRIC_DIV = 1;
 208
 209         initial CLKOUT_PREDIV = 0;
 210         initial CLKOUT_FABRIC = 0;
 211
 212         //output dividers not implemented for simulation
 213         //auto powerdown not implemented for simulation
 214
 215         always begin
 216                 if(PWRDN) begin
 217                         CLKOUT_PREDIV = 0;
 218                         CLKOUT_FABRIC = 0;
 219                 end
 220                 else begin
 221                         //half period of 27 MHz
 222                         #18.518;
 223                         CLKOUT_PREDIV = ~CLKOUT_PREDIV;
 224                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
 225                 end
 226         end
 227
 228 endmodule
 229
 230 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 231
 232         parameter OUTA_DELAY = 1;
 233         parameter OUTA_INVERT = 0;
 234         parameter OUTB_DELAY = 1;
 235
 236         reg[15:0] shreg = 0;
 237
 238         always @(posedge clk, negedge RSTN) begin
 239
 240                 if(!nRST)
 241                         shreg = 0;
 242
 243                 else
 244                         shreg <= {shreg[14:0], IN};
 245
 246         end
 247
 248         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1];
 249         assign OUTB = shreg[OUTB_DELAY - 1];
 250
 251 endmodule
 252
 253 //keep constraint needed to prevent optimization since we have no outputs
 254 (* keep *)
 255 module GP_SYSRESET(input RST);
 256         parameter RESET_MODE = "RISING";
 257
 258         //cannot simulate whole system reset
 259
 260 endmodule
 261
 262 module GP_VDD(output OUT);
 263        assign OUT = 1;
 264 endmodule
 265
 266 module GP_VSS(output OUT);
 267        assign OUT = 0;
 268 endmodule