techlibs/greenpak4/cells_sim_ams.v

   1 `timescale 1ns/1ps
   2
   3 /*
   4  This file contains analog / mixed signal cells, or other things that are not possible to fully model
   5  in behavioral Verilog.
   6
   7  It also contains some stuff like oscillators that use non-synthesizeable constructs such as delays.
   8  TODO: do we want a third file for those cells?
   9  */
  10
  11 module GP_ABUF(input wire IN, output wire OUT);
  12
  13         assign OUT = IN;
  14
  15         //must be 1, 5, 20, 50
  16         //values >1 only available with Vdd > 2.7V
  17         parameter BANDWIDTH_KHZ = 1;
  18
  19 endmodule
  20
  21 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
  22
  23         parameter BANDWIDTH = "HIGH";
  24         parameter VIN_ATTEN = 1;
  25         parameter VIN_ISRC_EN = 0;
  26         parameter HYSTERESIS = 0;
  27
  28         initial OUT = 0;
  29
  30 endmodule
  31
  32 module GP_BANDGAP(output reg OK);
  33         parameter AUTO_PWRDN = 1;
  34         parameter CHOPPER_EN = 1;
  35         parameter OUT_DELAY = 100;
  36
  37 endmodule
  38
  39 module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
  40
  41         initial VOUT = 0;
  42
  43         //analog hard IP is not supported for simulation
  44
  45 endmodule
  46
  47 module GP_LFOSC(input PWRDN, output reg CLKOUT);
  48
  49         parameter PWRDN_EN = 0;
  50         parameter AUTO_PWRDN = 0;
  51         parameter OUT_DIV = 1;
  52
  53         initial CLKOUT = 0;
  54
  55         //auto powerdown not implemented for simulation
  56         //output dividers not implemented for simulation
  57
  58         always begin
  59                 if(PWRDN)
  60                         CLKOUT = 0;
  61                 else begin
  62                         //half period of 1730 Hz
  63                         #289017;
  64                         CLKOUT = ~CLKOUT;
  65                 end
  66         end
  67
  68 endmodule
  69
  70 module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
  71
  72         parameter GAIN = 1;
  73         parameter INPUT_MODE = "SINGLE";
  74
  75         initial VOUT = 0;
  76
  77         //cannot simulate mixed signal IP
  78
  79 endmodule
  80
  81 module GP_PWRDET(output reg VDD_LOW);
  82         initial VDD_LOW = 0;
  83 endmodule
  84
  85 module GP_VREF(input VIN, output reg VOUT);
  86         parameter VIN_DIV = 1;
  87         parameter VREF = 0;
  88         //cannot simulate mixed signal IP
  89 endmodule
  90
  91 module GP_POR(output reg RST_DONE);
  92         parameter POR_TIME = 500;
  93
  94         initial begin
  95                 RST_DONE = 0;
  96
  97                 if(POR_TIME == 4)
  98                         #4000;
  99                 else if(POR_TIME == 500)
 100                         #500000;
 101                 else begin
 102                         $display("ERROR: bad POR_TIME for GP_POR cell");
 103                         $finish;
 104                 end
 105
 106                 RST_DONE = 1;
 107
 108         end
 109
 110 endmodule