4 This file contains simulation models for GreenPAK cells which are possible to fully model using synthesizeable
5 behavioral Verilog constructs only.
8 module GP_2LUT(input IN0, IN1, output OUT);
9 parameter [3:0] INIT = 0;
10 assign OUT = INIT[{IN1, IN0}];
13 module GP_3LUT(input IN0, IN1, IN2, output OUT);
14 parameter [7:0] INIT = 0;
15 assign OUT = INIT[{IN2, IN1, IN0}];
25 parameter [15:0] INIT = 0;
26 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
29 module GP_CLKBUF(input wire IN, output wire OUT);
33 module GP_COUNT14(input CLK, input wire RST, output reg OUT);
35 parameter RESET_MODE = "RISING";
37 parameter COUNT_TO = 14'h1;
38 parameter CLKIN_DIVIDE = 1;
40 reg[13:0] count = COUNT_TO;
43 if(CLKIN_DIVIDE != 1) begin
44 $display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
49 //Combinatorially output underflow flag whenever we wrap low
51 OUT <= (count == 14'h0);
54 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
55 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
60 always @(posedge CLK, posedge RST) begin
61 count <= count - 1'd1;
71 always @(posedge CLK, negedge RST) begin
72 count <= count - 1'd1;
83 $display("Both-edge reset mode for GP_COUNT14 not implemented");
89 always @(posedge CLK, posedge RST) begin
94 count <= count - 1'd1;
103 $display("Invalid RESET_MODE on GP_COUNT8");
113 module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
114 input UP, input KEEP, output reg[7:0] POUT);
116 parameter RESET_MODE = "RISING";
117 parameter RESET_VALUE = "ZERO";
119 parameter COUNT_TO = 14'h1;
120 parameter CLKIN_DIVIDE = 1;
123 if(CLKIN_DIVIDE != 1) begin
124 $display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
129 reg[13:0] count = COUNT_TO;
131 //Combinatorially output underflow flag whenever we wrap low
134 OUT <= (count == 14'h3fff);
136 OUT <= (count == 14'h0);
140 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
141 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
146 always @(posedge CLK, posedge RST) begin
152 count <= count + 1'd1;
154 count <= count - 1'd1;
157 if(count == 0 && !UP)
159 if(count == 14'h3fff && UP)
164 if(RESET_VALUE == "ZERO")
174 always @(posedge CLK, negedge RST) begin
180 count <= count + 1'd1;
182 count <= count - 1'd1;
185 if(count == 0 && !UP)
187 if(count == 14'h3fff && UP)
192 if(RESET_VALUE == "ZERO")
203 $display("Both-edge reset mode for GP_COUNT14_ADV not implemented");
209 always @(posedge CLK, posedge RST) begin
213 if(RESET_VALUE == "ZERO")
225 count <= count + 1'd1;
227 count <= count - 1'd1;
230 if(count == 0 && !UP)
232 if(count == 14'h3fff && UP)
242 $display("Invalid RESET_MODE on GP_COUNT14_ADV");
252 module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
253 input UP, input KEEP, output reg[7:0] POUT);
255 parameter RESET_MODE = "RISING";
256 parameter RESET_VALUE = "ZERO";
258 parameter COUNT_TO = 8'h1;
259 parameter CLKIN_DIVIDE = 1;
261 reg[7:0] count = COUNT_TO;
264 if(CLKIN_DIVIDE != 1) begin
265 $display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
270 //Combinatorially output underflow flag whenever we wrap low
273 OUT <= (count == 8'hff);
275 OUT <= (count == 8'h0);
279 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
280 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
285 always @(posedge CLK, posedge RST) begin
291 count <= count + 1'd1;
293 count <= count - 1'd1;
296 if(count == 0 && !UP)
298 if(count == 8'hff && UP)
303 if(RESET_VALUE == "ZERO")
313 always @(posedge CLK, negedge RST) begin
319 count <= count + 1'd1;
321 count <= count - 1'd1;
324 if(count == 0 && !UP)
326 if(count == 8'hff && UP)
331 if(RESET_VALUE == "ZERO")
342 $display("Both-edge reset mode for GP_COUNT8_ADV not implemented");
348 always @(posedge CLK, posedge RST) begin
352 if(RESET_VALUE == "ZERO")
364 count <= count + 1'd1;
366 count <= count - 1'd1;
369 if(count == 0 && !UP)
371 if(count == 8'hff && UP)
381 $display("Invalid RESET_MODE on GP_COUNT8_ADV");
395 output reg[7:0] POUT);
397 parameter RESET_MODE = "RISING";
399 parameter COUNT_TO = 8'h1;
400 parameter CLKIN_DIVIDE = 1;
403 if(CLKIN_DIVIDE != 1) begin
404 $display("ERROR: CLKIN_DIVIDE values other than 1 not implemented");
409 reg[7:0] count = COUNT_TO;
411 //Combinatorially output underflow flag whenever we wrap low
413 OUT <= (count == 8'h0);
417 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
418 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
423 always @(posedge CLK, posedge RST) begin
424 count <= count - 1'd1;
434 always @(posedge CLK, negedge RST) begin
435 count <= count - 1'd1;
446 $display("Both-edge reset mode for GP_COUNT8 not implemented");
452 always @(posedge CLK, posedge RST) begin
457 count <= count - 1'd1;
466 $display("Invalid RESET_MODE on GP_COUNT8");
476 module GP_DCMPREF(output reg[7:0]OUT);
477 parameter[7:0] REF_VAL = 8'h00;
478 initial OUT = REF_VAL;
481 module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
509 module GP_DELAY(input IN, output reg OUT);
511 parameter DELAY_STEPS = 1;
512 parameter GLITCH_FILTER = 0;
518 if(GLITCH_FILTER) begin
520 $display("ERROR: GP_DELAY glitch filter mode not implemented");
525 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
526 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
534 $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
544 module GP_DFF(input D, CLK, output reg Q);
545 parameter [0:0] INIT = 1'bx;
547 always @(posedge CLK) begin
552 module GP_DFFI(input D, CLK, output reg nQ);
553 parameter [0:0] INIT = 1'bx;
555 always @(posedge CLK) begin
560 module GP_DFFR(input D, CLK, nRST, output reg Q);
561 parameter [0:0] INIT = 1'bx;
563 always @(posedge CLK, negedge nRST) begin
571 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
572 parameter [0:0] INIT = 1'bx;
574 always @(posedge CLK, negedge nRST) begin
582 module GP_DFFS(input D, CLK, nSET, output reg Q);
583 parameter [0:0] INIT = 1'bx;
585 always @(posedge CLK, negedge nSET) begin
593 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
594 parameter [0:0] INIT = 1'bx;
596 always @(posedge CLK, negedge nSET) begin
604 module GP_DFFSR(input D, CLK, nSR, output reg Q);
605 parameter [0:0] INIT = 1'bx;
606 parameter [0:0] SRMODE = 1'bx;
608 always @(posedge CLK, negedge nSR) begin
616 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
617 parameter [0:0] INIT = 1'bx;
618 parameter [0:0] SRMODE = 1'bx;
620 always @(posedge CLK, negedge nSR) begin
628 module GP_DLATCH(input D, input nCLK, output reg Q);
629 parameter [0:0] INIT = 1'bx;
637 module GP_DLATCHI(input D, input nCLK, output reg nQ);
638 parameter [0:0] INIT = 1'bx;
646 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
647 parameter [0:0] INIT = 1'bx;
657 module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
658 parameter [0:0] INIT = 1'bx;
668 module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
669 parameter [0:0] INIT = 1'bx;
679 module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
680 parameter [0:0] INIT = 1'bx;
690 module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
691 parameter [0:0] INIT = 1'bx;
692 parameter[0:0] SRMODE = 1'bx;
702 module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
703 parameter [0:0] INIT = 1'bx;
704 parameter[0:0] SRMODE = 1'bx;
714 module GP_IBUF(input IN, output OUT);
718 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
720 assign IO = OE ? IN : 1'bz;
723 module GP_INV(input IN, output OUT);
727 module GP_OBUF(input IN, output OUT);
731 module GP_OBUFT(input IN, input OE, output OUT);
732 assign OUT = OE ? IN : 1'bz;
735 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
737 parameter PATTERN_DATA = 16'h0;
738 parameter PATTERN_LEN = 5'd16;
741 always @(posedge CLK) begin
743 OUT <= PATTERN_DATA[0];
747 OUT <= PATTERN_DATA[count];
749 if( (count + 1) == PATTERN_LEN)
756 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
758 parameter OUTA_TAP = 1;
759 parameter OUTA_INVERT = 0;
760 parameter OUTB_TAP = 1;
764 always @(posedge CLK, negedge nRST) begin
770 shreg <= {shreg[14:0], IN};
774 assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
775 assign OUTB = shreg[OUTB_TAP - 1];
779 module GP_VDD(output OUT);
783 module GP_VSS(output OUT);