techlibs/greenpak4/cells_sim_digital.v

   1 `timescale 1ns/1ps
   2
   3 /*
   4  This file contains simulation models for GreenPAK cells which are possible to fully model using synthesizeable
   5  behavioral Verilog constructs only.
   6  */
   7
   8 module GP_2LUT(input IN0, IN1, output OUT);
   9         parameter [3:0] INIT = 0;
  10         assign OUT = INIT[{IN1, IN0}];
  11 endmodule
  12
  13 module GP_3LUT(input IN0, IN1, IN2, output OUT);
  14         parameter [7:0] INIT = 0;
  15         assign OUT = INIT[{IN2, IN1, IN0}];
  16 endmodule
  17
  18 module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
  19         parameter [15:0] INIT = 0;
  20         assign OUT = INIT[{IN3, IN2, IN1, IN0}];
  21 endmodule
  22
  23 module GP_CLKBUF(input wire IN, output wire OUT);
  24         assign OUT = IN;
  25 endmodule
  26
  27 module GP_DCMPREF(output reg[7:0]OUT);
  28         parameter[7:0] REF_VAL = 8'h00;
  29         initial OUT = REF_VAL;
  30 endmodule
  31
  32 module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
  33
  34         always @(*) begin
  35                 case(SEL)
  36                         2'd00: begin
  37                                 OUTA <= IN0;
  38                                 OUTB <= IN3;
  39                         end
  40
  41                         2'd01: begin
  42                                 OUTA <= IN1;
  43                                 OUTB <= IN2;
  44                         end
  45
  46                         2'd02: begin
  47                                 OUTA <= IN2;
  48                                 OUTB <= IN1;
  49                         end
  50
  51                         2'd03: begin
  52                                 OUTA <= IN3;
  53                                 OUTB <= IN0;
  54                         end
  55
  56                 endcase
  57         end
  58 endmodule
  59
  60 module GP_DELAY(input IN, output reg OUT);
  61
  62         parameter DELAY_STEPS = 1;
  63         parameter GLITCH_FILTER = 0;
  64
  65         initial OUT = 0;
  66
  67         generate
  68
  69                 if(GLITCH_FILTER) begin
  70                         initial begin
  71                                 $display("ERROR: GP_DELAY glitch filter mode not implemented");
  72                                 $finish;
  73                         end
  74                 end
  75
  76                 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
  77                 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
  78                 always @(*) begin
  79                         case(DELAY_STEPS)
  80                                 1: #166 OUT = IN;
  81                                 2: #318 OUT = IN;
  82                                 2: #471 OUT = IN;
  83                                 3: #622 OUT = IN;
  84                                 default: begin
  85                                         $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
  86                                         $finish;
  87                                 end
  88                         endcase
  89                 end
  90
  91         endgenerate
  92
  93 endmodule
  94
  95 module GP_DFF(input D, CLK, output reg Q);
  96         parameter [0:0] INIT = 1'bx;
  97         initial Q = INIT;
  98         always @(posedge CLK) begin
  99                 Q <= D;
 100         end
 101 endmodule
 102
 103 module GP_DFFI(input D, CLK, output reg nQ);
 104         parameter [0:0] INIT = 1'bx;
 105         initial nQ = INIT;
 106         always @(posedge CLK) begin
 107                 nQ <= ~D;
 108         end
 109 endmodule
 110
 111 module GP_DFFR(input D, CLK, nRST, output reg Q);
 112         parameter [0:0] INIT = 1'bx;
 113         initial Q = INIT;
 114         always @(posedge CLK, negedge nRST) begin
 115                 if (!nRST)
 116                         Q <= 1'b0;
 117                 else
 118                         Q <= D;
 119         end
 120 endmodule
 121
 122 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
 123         parameter [0:0] INIT = 1'bx;
 124         initial nQ = INIT;
 125         always @(posedge CLK, negedge nRST) begin
 126                 if (!nRST)
 127                         nQ <= 1'b1;
 128                 else
 129                         nQ <= ~D;
 130         end
 131 endmodule
 132
 133 module GP_DFFS(input D, CLK, nSET, output reg Q);
 134         parameter [0:0] INIT = 1'bx;
 135         initial Q = INIT;
 136         always @(posedge CLK, negedge nSET) begin
 137                 if (!nSET)
 138                         Q <= 1'b1;
 139                 else
 140                         Q <= D;
 141         end
 142 endmodule
 143
 144 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
 145         parameter [0:0] INIT = 1'bx;
 146         initial nQ = INIT;
 147         always @(posedge CLK, negedge nSET) begin
 148                 if (!nSET)
 149                         nQ <= 1'b0;
 150                 else
 151                         nQ <= ~D;
 152         end
 153 endmodule
 154
 155 module GP_DFFSR(input D, CLK, nSR, output reg Q);
 156         parameter [0:0] INIT = 1'bx;
 157         parameter [0:0] SRMODE = 1'bx;
 158         initial Q = INIT;
 159         always @(posedge CLK, negedge nSR) begin
 160                 if (!nSR)
 161                         Q <= SRMODE;
 162                 else
 163                         Q <= D;
 164         end
 165 endmodule
 166
 167 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
 168         parameter [0:0] INIT = 1'bx;
 169         parameter [0:0] SRMODE = 1'bx;
 170         initial nQ = INIT;
 171         always @(posedge CLK, negedge nSR) begin
 172                 if (!nSR)
 173                         nQ <= ~SRMODE;
 174                 else
 175                         nQ <= ~D;
 176         end
 177 endmodule
 178
 179 module GP_DLATCH(input D, input nCLK, output reg Q);
 180         parameter [0:0] INIT = 1'bx;
 181         initial Q = INIT;
 182         always @(*) begin
 183                 if(!nCLK)
 184                         Q <= D;
 185         end
 186 endmodule
 187
 188 module GP_DLATCHI(input D, input nCLK, output reg nQ);
 189         parameter [0:0] INIT = 1'bx;
 190         initial nQ = INIT;
 191         always @(*) begin
 192                 if(!nCLK)
 193                         nQ <= ~D;
 194         end
 195 endmodule
 196
 197 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
 198         parameter [0:0] INIT = 1'bx;
 199         initial Q = INIT;
 200         always @(*) begin
 201                 if(!nRST)
 202                         Q <= 1'b0;
 203                 else if(!nCLK)
 204                         Q <= D;
 205         end
 206 endmodule
 207
 208 module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
 209         parameter [0:0] INIT = 1'bx;
 210         initial nQ = INIT;
 211         always @(*) begin
 212                 if(!nRST)
 213                         nQ <= 1'b1;
 214                 else if(!nCLK)
 215                         nQ <= ~D;
 216         end
 217 endmodule
 218
 219 module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
 220         parameter [0:0] INIT = 1'bx;
 221         initial Q = INIT;
 222         always @(*) begin
 223                 if(!nSET)
 224                         Q <= 1'b1;
 225                 else if(!nCLK)
 226                         Q <= D;
 227         end
 228 endmodule
 229
 230 module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
 231         parameter [0:0] INIT = 1'bx;
 232         initial nQ = INIT;
 233         always @(*) begin
 234                 if(!nSET)
 235                         nQ <= 1'b0;
 236                 else if(!nCLK)
 237                         nQ <= ~D;
 238         end
 239 endmodule
 240
 241 module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
 242         parameter [0:0] INIT = 1'bx;
 243         parameter[0:0] SRMODE = 1'bx;
 244         initial Q = INIT;
 245         always @(*) begin
 246                 if(!nSR)
 247                         Q <= SRMODE;
 248                 else if(!nCLK)
 249                         Q <= D;
 250         end
 251 endmodule
 252
 253 module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
 254         parameter [0:0] INIT = 1'bx;
 255         parameter[0:0] SRMODE = 1'bx;
 256         initial nQ = INIT;
 257         always @(*) begin
 258                 if(!nSR)
 259                         nQ <= ~SRMODE;
 260                 else if(!nCLK)
 261                         nQ <= ~D;
 262         end
 263 endmodule
 264
 265 module GP_IBUF(input IN, output OUT);
 266         assign OUT = IN;
 267 endmodule
 268
 269 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
 270         assign OUT = IO;
 271         assign IO = OE ? IN : 1'bz;
 272 endmodule
 273
 274 module GP_INV(input IN, output OUT);
 275         assign OUT = ~IN;
 276 endmodule
 277
 278 module GP_OBUF(input IN, output OUT);
 279         assign OUT = IN;
 280 endmodule
 281
 282 module GP_OBUFT(input IN, input OE, output OUT);
 283         assign OUT = OE ? IN : 1'bz;
 284 endmodule
 285
 286 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
 287         initial OUT = 0;
 288         parameter PATTERN_DATA = 16'h0;
 289         parameter PATTERN_LEN = 5'd16;
 290
 291         reg[3:0] count = 0;
 292         always @(posedge CLK) begin
 293                 if(!nRST)
 294                         OUT <= PATTERN_DATA[0];
 295
 296                 else begin
 297                         count <= count + 1;
 298                         OUT <= PATTERN_DATA[count];
 299
 300                         if( (count + 1) == PATTERN_LEN)
 301                                 count <= 0;
 302                 end
 303         end
 304
 305 endmodule
 306
 307 module GP_POR(output reg RST_DONE);
 308         parameter POR_TIME = 500;
 309
 310         initial begin
 311                 RST_DONE = 0;
 312
 313                 if(POR_TIME == 4)
 314                         #4000;
 315                 else if(POR_TIME == 500)
 316                         #500000;
 317                 else begin
 318                         $display("ERROR: bad POR_TIME for GP_POR cell");
 319                         $finish;
 320                 end
 321
 322                 RST_DONE = 1;
 323
 324         end
 325
 326 endmodule
 327
 328 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
 329
 330         parameter OUTA_TAP = 1;
 331         parameter OUTA_INVERT = 0;
 332         parameter OUTB_TAP = 1;
 333
 334         reg[15:0] shreg = 0;
 335
 336         always @(posedge CLK, negedge nRST) begin
 337
 338                 if(!nRST)
 339                         shreg = 0;
 340
 341                 else
 342                         shreg <= {shreg[14:0], IN};
 343
 344         end
 345
 346         assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
 347         assign OUTB = shreg[OUTB_TAP - 1];
 348
 349 endmodule
 350
 351 module GP_VDD(output OUT);
 352        assign OUT = 1;
 353 endmodule
 354
 355 module GP_VSS(output OUT);
 356        assign OUT = 0;
 357 endmodule