4 This file contains simulation models for GreenPAK cells which are possible to fully model using synthesizeable
5 behavioral Verilog constructs only.
8 module GP_2LUT(input IN0, IN1, output OUT);
9 parameter [3:0] INIT = 0;
10 assign OUT = INIT[{IN1, IN0}];
13 module GP_3LUT(input IN0, IN1, IN2, output OUT);
14 parameter [7:0] INIT = 0;
15 assign OUT = INIT[{IN2, IN1, IN0}];
25 parameter [15:0] INIT = 0;
26 assign OUT = INIT[{IN3, IN2, IN1, IN0}];
29 module GP_CLKBUF(input wire IN, output wire OUT);
37 output reg[7:0] POUT);
39 parameter RESET_MODE = "RISING";
41 parameter COUNT_TO = 8'h1;
42 parameter CLKIN_DIVIDE = 1;
44 reg[7:0] count = COUNT_TO;
46 //Combinatorially output underflow flag whenever we wrap low
48 OUT <= (count == 8'h0);
52 //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
53 //Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
58 always @(posedge CLK or posedge RST) begin
59 count <= count - 1'd1;
69 always @(posedge CLK or negedge RST) begin
70 count <= count - 1'd1;
81 $display("Both-edge reset mode for GP_COUNT8 not implemented");
91 $display("Invalid RESET_MODE on GP_COUNT8");
101 module GP_DCMPREF(output reg[7:0]OUT);
102 parameter[7:0] REF_VAL = 8'h00;
103 initial OUT = REF_VAL;
106 module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2, input[7:0] IN3, output reg[7:0] OUTA, output reg[7:0] OUTB);
134 module GP_DELAY(input IN, output reg OUT);
136 parameter DELAY_STEPS = 1;
137 parameter GLITCH_FILTER = 0;
143 if(GLITCH_FILTER) begin
145 $display("ERROR: GP_DELAY glitch filter mode not implemented");
150 //TODO: These delays are PTV dependent! For now, hard code 3v3 timing
151 //Change simulation-mode delay depending on global Vdd range (how to specify this?)
159 $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]");
169 module GP_DFF(input D, CLK, output reg Q);
170 parameter [0:0] INIT = 1'bx;
172 always @(posedge CLK) begin
177 module GP_DFFI(input D, CLK, output reg nQ);
178 parameter [0:0] INIT = 1'bx;
180 always @(posedge CLK) begin
185 module GP_DFFR(input D, CLK, nRST, output reg Q);
186 parameter [0:0] INIT = 1'bx;
188 always @(posedge CLK, negedge nRST) begin
196 module GP_DFFRI(input D, CLK, nRST, output reg nQ);
197 parameter [0:0] INIT = 1'bx;
199 always @(posedge CLK, negedge nRST) begin
207 module GP_DFFS(input D, CLK, nSET, output reg Q);
208 parameter [0:0] INIT = 1'bx;
210 always @(posedge CLK, negedge nSET) begin
218 module GP_DFFSI(input D, CLK, nSET, output reg nQ);
219 parameter [0:0] INIT = 1'bx;
221 always @(posedge CLK, negedge nSET) begin
229 module GP_DFFSR(input D, CLK, nSR, output reg Q);
230 parameter [0:0] INIT = 1'bx;
231 parameter [0:0] SRMODE = 1'bx;
233 always @(posedge CLK, negedge nSR) begin
241 module GP_DFFSRI(input D, CLK, nSR, output reg nQ);
242 parameter [0:0] INIT = 1'bx;
243 parameter [0:0] SRMODE = 1'bx;
245 always @(posedge CLK, negedge nSR) begin
253 module GP_DLATCH(input D, input nCLK, output reg Q);
254 parameter [0:0] INIT = 1'bx;
262 module GP_DLATCHI(input D, input nCLK, output reg nQ);
263 parameter [0:0] INIT = 1'bx;
271 module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
272 parameter [0:0] INIT = 1'bx;
282 module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
283 parameter [0:0] INIT = 1'bx;
293 module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
294 parameter [0:0] INIT = 1'bx;
304 module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
305 parameter [0:0] INIT = 1'bx;
315 module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
316 parameter [0:0] INIT = 1'bx;
317 parameter[0:0] SRMODE = 1'bx;
327 module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
328 parameter [0:0] INIT = 1'bx;
329 parameter[0:0] SRMODE = 1'bx;
339 module GP_IBUF(input IN, output OUT);
343 module GP_IOBUF(input IN, input OE, output OUT, inout IO);
345 assign IO = OE ? IN : 1'bz;
348 module GP_INV(input IN, output OUT);
352 module GP_OBUF(input IN, output OUT);
356 module GP_OBUFT(input IN, input OE, output OUT);
357 assign OUT = OE ? IN : 1'bz;
360 module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
362 parameter PATTERN_DATA = 16'h0;
363 parameter PATTERN_LEN = 5'd16;
366 always @(posedge CLK) begin
368 OUT <= PATTERN_DATA[0];
372 OUT <= PATTERN_DATA[count];
374 if( (count + 1) == PATTERN_LEN)
381 module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
383 parameter OUTA_TAP = 1;
384 parameter OUTA_INVERT = 0;
385 parameter OUTB_TAP = 1;
389 always @(posedge CLK, negedge nRST) begin
395 shreg <= {shreg[14:0], IN};
399 assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
400 assign OUTB = shreg[OUTB_TAP - 1];
404 module GP_VDD(output OUT);
408 module GP_VSS(output OUT);