techlibs/greenpak4/cells_sim_wip.v

   1
   2 //Cells still in this file have INCOMPLETE simulation models, need to finish them
   3
   4 module GP_DCMP(input[7:0] INP, input[7:0] INN, input CLK, input PWRDN, output reg GREATER, output reg EQUAL);
   5         parameter PWRDN_SYNC = 1'b0;
   6         parameter CLK_EDGE = "RISING";
   7         parameter GREATER_OR_EQUAL = 1'b0;
   8
   9         //TODO implement power-down mode
  10
  11         initial GREATER = 0;
  12         initial EQUAL = 0;
  13
  14         wire clk_minv = (CLK_EDGE == "RISING") ? CLK : ~CLK;
  15         always @(posedge clk_minv) begin
  16                 if(GREATER_OR_EQUAL)
  17                         GREATER <= (INP >= INN);
  18                 else
  19                         GREATER <= (INP > INN);
  20
  21                 EQUAL <= (INP == INN);
  22         end
  23
  24 endmodule
  25
  26 module GP_EDGEDET(input IN, output reg OUT);
  27
  28         parameter EDGE_DIRECTION = "RISING";
  29         parameter DELAY_STEPS = 1;
  30         parameter GLITCH_FILTER = 0;
  31
  32         //not implemented for simulation
  33
  34 endmodule
  35
  36 module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
  37
  38         parameter PWRDN_EN = 0;
  39         parameter AUTO_PWRDN = 0;
  40         parameter HARDIP_DIV = 1;
  41         parameter FABRIC_DIV = 1;
  42         parameter OSC_FREQ = "25k";
  43
  44         initial CLKOUT_HARDIP = 0;
  45         initial CLKOUT_FABRIC = 0;
  46
  47         //output dividers not implemented for simulation
  48         //auto powerdown not implemented for simulation
  49
  50         always begin
  51                 if(PWRDN) begin
  52                         CLKOUT_HARDIP = 0;
  53                         CLKOUT_FABRIC = 0;
  54                 end
  55                 else begin
  56
  57                         if(OSC_FREQ == "25k") begin
  58                                 //half period of 25 kHz
  59                                 #20000;
  60                         end
  61
  62                         else begin
  63                                 //half period of 2 MHz
  64                                 #250;
  65                         end
  66
  67                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
  68                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
  69                 end
  70         end
  71
  72 endmodule
  73
  74 module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC);
  75
  76         parameter PWRDN_EN = 0;
  77         parameter AUTO_PWRDN = 0;
  78         parameter HARDIP_DIV = 1;
  79         parameter FABRIC_DIV = 1;
  80
  81         initial CLKOUT_HARDIP = 0;
  82         initial CLKOUT_FABRIC = 0;
  83
  84         //output dividers not implemented for simulation
  85         //auto powerdown not implemented for simulation
  86
  87         always begin
  88                 if(PWRDN) begin
  89                         CLKOUT_HARDIP = 0;
  90                         CLKOUT_FABRIC = 0;
  91                 end
  92                 else begin
  93                         //half period of 27 MHz
  94                         #18.518;
  95                         CLKOUT_HARDIP = ~CLKOUT_HARDIP;
  96                         CLKOUT_FABRIC = ~CLKOUT_FABRIC;
  97                 end
  98         end
  99
 100 endmodule
 101
 102 module GP_SPI(
 103         input SCK,
 104         inout SDAT,
 105         input CSN,
 106         input[7:0] TXD_HIGH,
 107         input[7:0] TXD_LOW,
 108         output reg[7:0] RXD_HIGH,
 109         output reg[7:0] RXD_LOW,
 110         output reg INT);
 111
 112         initial RXD_HIGH = 0;
 113         initial RXD_LOW = 0;
 114         initial INT = 0;
 115
 116         parameter DATA_WIDTH = 8;               //byte or word width
 117         parameter SPI_CPHA = 0;                 //SPI clock phase
 118         parameter SPI_CPOL = 0;                 //SPI clock polarity
 119         parameter DIRECTION = "INPUT";  //SPI data direction (either input to chip or output to host)
 120         //parallel output to fabric not yet implemented
 121
 122         //TODO: write sim model
 123         //TODO: SPI SDIO control... can we use ADC output while SPI is input??
 124         //TODO: clock sync
 125
 126 endmodule
 127
 128 //keep constraint needed to prevent optimization since we have no outputs
 129 (* keep *)
 130 module GP_SYSRESET(input RST);
 131         parameter RESET_MODE = "EDGE";
 132         parameter EDGE_SPEED = 4;
 133
 134         //cannot simulate whole system reset
 135
 136 endmodule