techlibs/greenpak4/synth_greenpak4.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 bool check_label(bool &active, std::string run_from, std::string run_to, std::string label)
  29 {
  30         if (label == run_from)
  31                 active = true;
  32         if (label == run_to)
  33                 active = false;
  34         return active;
  35 }
  36
  37 struct SynthGreenPAK4Pass : public Pass {
  38         SynthGreenPAK4Pass() : Pass("synth_greenpak4", "synthesis for GreenPAK4 FPGAs") { }
  39         virtual void help()
  40         {
  41                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  42                 log("\n");
  43                 log("    synth_greenpak4 [options]\n");
  44                 log("\n");
  45                 log("This command runs synthesis for GreenPAK4 FPGAs. This work is experimental.\n");
  46                 log("\n");
  47                 log("    -top <module>\n");
  48                 log("        use the specified module as top module (default='top')\n");
  49                 log("\n");
  50                 log("    -part <part>\n");
  51                 log("        synthesize for the specified part. Valid values are SLG46140V,\n");
  52                 log("        SLG46620V, and SLG46621V (default).\n");
  53                 log("\n");
  54                 log("    -json <file>\n");
  55                 log("        write the design to the specified JSON file. writing of an output file\n");
  56                 log("        is omitted if this parameter is not specified.\n");
  57                 log("\n");
  58                 log("    -run <from_label>:<to_label>\n");
  59                 log("        only run the commands between the labels (see below). an empty\n");
  60                 log("        from label is synonymous to 'begin', and empty to label is\n");
  61                 log("        synonymous to the end of the command list.\n");
  62                 log("\n");
  63                 log("    -noflatten\n");
  64                 log("        do not flatten design before synthesis\n");
  65                 log("\n");
  66                 log("    -retime\n");
  67                 log("        run 'abc' with -dff option\n");
  68                 log("\n");
  69                 log("\n");
  70                 log("The following commands are executed by this synthesis command:\n");
  71                 log("\n");
  72                 log("    begin:\n");
  73                 log("        read_verilog -lib +/greenpak4/cells_sim.v\n");
  74                 log("        hierarchy -check -top <top>\n");
  75                 log("\n");
  76                 log("    flatten:         (unless -noflatten)\n");
  77                 log("        proc\n");
  78                 log("        flatten\n");
  79                 log("        tribuf -logic\n");
  80                 log("\n");
  81                 log("    coarse:\n");
  82                 log("        synth -run coarse\n");
  83                 log("\n");
  84                 log("    fine:\n");
  85                 log("        opt -fast -mux_undef -undriven -fine\n");
  86                 log("        memory_map\n");
  87                 log("        opt -undriven -fine\n");
  88                 log("        techmap\n");
  89                 log("        dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib\n");
  90                 log("        opt -fast\n");
  91                 log("        abc -dff     (only if -retime)\n");
  92                 log("\n");
  93                 log("    map_luts:\n");
  94                 log("        nlutmap -luts 0,6,8,2        (for -part SLG46140V)\n");
  95                 log("        nlutmap -luts 0,8,16,2       (for -part SLG46620V)\n");
  96                 log("        nlutmap -luts 0,8,16,2       (for -part SLG46621V)\n");
  97                 log("        clean\n");
  98                 log("\n");
  99                 log("    map_cells:\n");
 100                 log("        techmap -map +/greenpak4/cells_map.v\n");
 101                 log("        clean\n");
 102                 log("\n");
 103                 log("    check:\n");
 104                 log("        hierarchy -check\n");
 105                 log("        stat\n");
 106                 log("        check -noinit\n");
 107                 log("\n");
 108                 log("    json:\n");
 109                 log("        write_json <file-name>\n");
 110                 log("\n");
 111         }
 112         virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 113         {
 114                 std::string top_opt = "-auto-top";
 115                 std::string part = "SLG46621V";
 116                 std::string run_from, run_to;
 117                 std::string json_file;
 118                 bool flatten = true;
 119                 bool retime = false;
 120
 121                 size_t argidx;
 122                 for (argidx = 1; argidx < args.size(); argidx++)
 123                 {
 124                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
 125                                 top_opt = "-top " + args[++argidx];
 126                                 continue;
 127                         }
 128                         if (args[argidx] == "-json" && argidx+1 < args.size()) {
 129                                 json_file = args[++argidx];
 130                                 continue;
 131                         }
 132                         if (args[argidx] == "-part" && argidx+1 < args.size()) {
 133                                 part = args[++argidx];
 134                                 continue;
 135                         }
 136                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 137                                 size_t pos = args[argidx+1].find(':');
 138                                 if (pos == std::string::npos)
 139                                         break;
 140                                 run_from = args[++argidx].substr(0, pos);
 141                                 run_to = args[argidx].substr(pos+1);
 142                                 continue;
 143                         }
 144                         if (args[argidx] == "-noflatten") {
 145                                 flatten = false;
 146                                 continue;
 147                         }
 148                         if (args[argidx] == "-retime") {
 149                                 retime = true;
 150                                 continue;
 151                         }
 152                         break;
 153                 }
 154                 extra_args(args, argidx, design);
 155
 156                 if (!design->full_selection())
 157                         log_cmd_error("This comannd only operates on fully selected designs!\n");
 158
 159                 if (part != "SLG46140V" && part != "SLG46620V" && part != "SLG46621V")
 160                         log_cmd_error("Invalid part name: '%s'\n", part.c_str());
 161
 162                 bool active = run_from.empty();
 163
 164                 log_header("Executing SYNTH_GREENPAK4 pass.\n");
 165                 log_push();
 166
 167                 if (check_label(active, run_from, run_to, "begin"))
 168                 {
 169                         Pass::call(design, "read_verilog -lib +/greenpak4/cells_sim.v");
 170                         Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
 171                 }
 172
 173                 if (flatten && check_label(active, run_from, run_to, "flatten"))
 174                 {
 175                         Pass::call(design, "proc");
 176                         Pass::call(design, "flatten");
 177                         Pass::call(design, "tribuf -logic");
 178                 }
 179
 180                 if (check_label(active, run_from, run_to, "coarse"))
 181                 {
 182                         Pass::call(design, "synth -run coarse");
 183                 }
 184
 185                 if (check_label(active, run_from, run_to, "fine"))
 186                 {
 187                         Pass::call(design, "opt -fast -mux_undef -undriven -fine");
 188                         Pass::call(design, "memory_map");
 189                         Pass::call(design, "opt -undriven -fine");
 190                         Pass::call(design, "techmap");
 191                         Pass::call(design, "dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
 192                         Pass::call(design, "opt -fast");
 193                         if (retime)
 194                                 Pass::call(design, "abc -dff");
 195                 }
 196
 197                 if (check_label(active, run_from, run_to, "map_luts"))
 198                 {
 199                         if (part == "SLG46140V") Pass::call(design, "nlutmap -luts 0,6,8,2");
 200                         if (part == "SLG46620V") Pass::call(design, "nlutmap -luts 0,8,16,2");
 201                         if (part == "SLG46621V") Pass::call(design, "nlutmap -luts 0,8,16,2");
 202                         Pass::call(design, "clean");
 203                 }
 204
 205                 if (check_label(active, run_from, run_to, "map_cells"))
 206                 {
 207                         Pass::call(design, "techmap -map +/greenpak4/cells_map.v");
 208                         Pass::call(design, "clean");
 209                 }
 210
 211                 if (check_label(active, run_from, run_to, "check"))
 212                 {
 213                         Pass::call(design, "hierarchy -check");
 214                         Pass::call(design, "stat");
 215                         Pass::call(design, "check -noinit");
 216                 }
 217
 218                 if (check_label(active, run_from, run_to, "json"))
 219                 {
 220                         if (!json_file.empty())
 221                                 Pass::call(design, stringf("write_json %s", json_file.c_str()));
 222                 }
 223
 224                 log_pop();
 225         }
 226 } SynthGreenPAK4Pass;
 227
 228 PRIVATE_NAMESPACE_END