2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/register.h"
21 #include "kernel/celltypes.h"
22 #include "kernel/rtlil.h"
23 #include "kernel/log.h"
26 PRIVATE_NAMESPACE_BEGIN
28 bool check_label(bool &active
, std::string run_from
, std::string run_to
, std::string label
)
30 if (label
== run_from
)
37 struct SynthGreenPAK4Pass
: public Pass
{
38 SynthGreenPAK4Pass() : Pass("synth_greenpak4", "synthesis for GreenPAK4 FPGAs") { }
41 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
43 log(" synth_greenpak4 [options]\n");
45 log("This command runs synthesis for GreenPAK4 FPGAs. This work is experimental.\n");
47 log(" -top <module>\n");
48 log(" use the specified module as top module (default='top')\n");
50 log(" -part <part>\n");
51 log(" synthesize for the specified part. Valid values are SLG46140V,\n");
52 log(" SLG46620V, and SLG46621V (default).\n");
54 log(" -json <file>\n");
55 log(" write the design to the specified JSON file. writing of an output file\n");
56 log(" is omitted if this parameter is not specified.\n");
58 log(" -run <from_label>:<to_label>\n");
59 log(" only run the commands between the labels (see below). an empty\n");
60 log(" from label is synonymous to 'begin', and empty to label is\n");
61 log(" synonymous to the end of the command list.\n");
64 log(" do not flatten design before synthesis\n");
67 log(" run 'abc' with -dff option\n");
70 log("The following commands are executed by this synthesis command:\n");
73 log(" read_verilog -lib +/greenpak4/cells_sim.v\n");
74 log(" hierarchy -check -top <top>\n");
76 log(" flatten: (unless -noflatten)\n");
79 log(" tribuf -logic\n");
82 log(" synth -run coarse\n");
85 log(" opt -fast -mux_undef -undriven -fine\n");
87 log(" opt -undriven -fine\n");
89 log(" dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib\n");
91 log(" abc -dff (only if -retime)\n");
94 log(" nlutmap -luts 0,6,8,2 (for -part SLG46140V)\n");
95 log(" nlutmap -luts 0,8,16,2 (for -part SLG46620V)\n");
96 log(" nlutmap -luts 0,8,16,2 (for -part SLG46621V)\n");
100 log(" techmap -map +/greenpak4/cells_map.v\n");
104 log(" hierarchy -check\n");
106 log(" check -noinit\n");
109 log(" write_json <file-name>\n");
112 virtual void execute(std::vector
<std::string
> args
, RTLIL::Design
*design
)
114 std::string top_opt
= "-auto-top";
115 std::string part
= "SLG46621V";
116 std::string run_from
, run_to
;
117 std::string json_file
;
122 for (argidx
= 1; argidx
< args
.size(); argidx
++)
124 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
125 top_opt
= "-top " + args
[++argidx
];
128 if (args
[argidx
] == "-json" && argidx
+1 < args
.size()) {
129 json_file
= args
[++argidx
];
132 if (args
[argidx
] == "-part" && argidx
+1 < args
.size()) {
133 part
= args
[++argidx
];
136 if (args
[argidx
] == "-run" && argidx
+1 < args
.size()) {
137 size_t pos
= args
[argidx
+1].find(':');
138 if (pos
== std::string::npos
)
140 run_from
= args
[++argidx
].substr(0, pos
);
141 run_to
= args
[argidx
].substr(pos
+1);
144 if (args
[argidx
] == "-noflatten") {
148 if (args
[argidx
] == "-retime") {
154 extra_args(args
, argidx
, design
);
156 if (!design
->full_selection())
157 log_cmd_error("This comannd only operates on fully selected designs!\n");
159 if (part
!= "SLG46140V" && part
!= "SLG46620V" && part
!= "SLG46621V")
160 log_cmd_error("Invalid part name: '%s'\n", part
.c_str());
162 bool active
= run_from
.empty();
164 log_header("Executing SYNTH_GREENPAK4 pass.\n");
167 if (check_label(active
, run_from
, run_to
, "begin"))
169 Pass::call(design
, "read_verilog -lib +/greenpak4/cells_sim.v");
170 Pass::call(design
, stringf("hierarchy -check %s", top_opt
.c_str()));
173 if (flatten
&& check_label(active
, run_from
, run_to
, "flatten"))
175 Pass::call(design
, "proc");
176 Pass::call(design
, "flatten");
177 Pass::call(design
, "tribuf -logic");
180 if (check_label(active
, run_from
, run_to
, "coarse"))
182 Pass::call(design
, "synth -run coarse");
185 if (check_label(active
, run_from
, run_to
, "fine"))
187 Pass::call(design
, "opt -fast -mux_undef -undriven -fine");
188 Pass::call(design
, "memory_map");
189 Pass::call(design
, "opt -undriven -fine");
190 Pass::call(design
, "techmap");
191 Pass::call(design
, "dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
192 Pass::call(design
, "opt -fast");
194 Pass::call(design
, "abc -dff");
197 if (check_label(active
, run_from
, run_to
, "map_luts"))
199 if (part
== "SLG46140V") Pass::call(design
, "nlutmap -luts 0,6,8,2");
200 if (part
== "SLG46620V") Pass::call(design
, "nlutmap -luts 0,8,16,2");
201 if (part
== "SLG46621V") Pass::call(design
, "nlutmap -luts 0,8,16,2");
202 Pass::call(design
, "clean");
205 if (check_label(active
, run_from
, run_to
, "map_cells"))
207 Pass::call(design
, "techmap -map +/greenpak4/cells_map.v");
208 Pass::call(design
, "clean");
211 if (check_label(active
, run_from
, run_to
, "check"))
213 Pass::call(design
, "hierarchy -check");
214 Pass::call(design
, "stat");
215 Pass::call(design
, "check -noinit");
218 if (check_label(active
, run_from
, run_to
, "json"))
220 if (!json_file
.empty())
221 Pass::call(design
, stringf("write_json %s", json_file
.c_str()));
226 } SynthGreenPAK4Pass
;
228 PRIVATE_NAMESPACE_END