techlibs/greenpak4/synth_greenpak4.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/register.h"
  21 #include "kernel/celltypes.h"
  22 #include "kernel/rtlil.h"
  23 #include "kernel/log.h"
  24
  25 USING_YOSYS_NAMESPACE
  26 PRIVATE_NAMESPACE_BEGIN
  27
  28 struct SynthGreenPAK4Pass : public ScriptPass
  29 {
  30         SynthGreenPAK4Pass() : ScriptPass("synth_greenpak4", "synthesis for GreenPAK4 FPGAs") { }
  31
  32         void help() YS_OVERRIDE
  33         {
  34                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  35                 log("\n");
  36                 log("    synth_greenpak4 [options]\n");
  37                 log("\n");
  38                 log("This command runs synthesis for GreenPAK4 FPGAs. This work is experimental.\n");
  39                 log("It is intended to be used with https://github.com/azonenberg/openfpga as the\n");
  40                 log("place-and-route.\n");
  41                 log("\n");
  42                 log("    -top <module>\n");
  43                 log("        use the specified module as top module (default='top')\n");
  44                 log("\n");
  45                 log("    -part <part>\n");
  46                 log("        synthesize for the specified part. Valid values are SLG46140V,\n");
  47                 log("        SLG46620V, and SLG46621V (default).\n");
  48                 log("\n");
  49                 log("    -json <file>\n");
  50                 log("        write the design to the specified JSON file. writing of an output file\n");
  51                 log("        is omitted if this parameter is not specified.\n");
  52                 log("\n");
  53                 log("    -run <from_label>:<to_label>\n");
  54                 log("        only run the commands between the labels (see below). an empty\n");
  55                 log("        from label is synonymous to 'begin', and empty to label is\n");
  56                 log("        synonymous to the end of the command list.\n");
  57                 log("\n");
  58                 log("    -noflatten\n");
  59                 log("        do not flatten design before synthesis\n");
  60                 log("\n");
  61                 log("    -retime\n");
  62                 log("        run 'abc' with '-dff -D 1' options\n");
  63                 log("\n");
  64                 log("\n");
  65                 log("The following commands are executed by this synthesis command:\n");
  66                 help_script();
  67                 log("\n");
  68         }
  69
  70         string top_opt, part, json_file;
  71         bool flatten, retime;
  72
  73         void clear_flags() YS_OVERRIDE
  74         {
  75                 top_opt = "-auto-top";
  76                 part = "SLG46621V";
  77                 json_file = "";
  78                 flatten = true;
  79                 retime = false;
  80         }
  81
  82         void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  83         {
  84                 string run_from, run_to;
  85                 clear_flags();
  86
  87                 size_t argidx;
  88                 for (argidx = 1; argidx < args.size(); argidx++)
  89                 {
  90                         if (args[argidx] == "-top" && argidx+1 < args.size()) {
  91                                 top_opt = "-top " + args[++argidx];
  92                                 continue;
  93                         }
  94                         if (args[argidx] == "-json" && argidx+1 < args.size()) {
  95                                 json_file = args[++argidx];
  96                                 continue;
  97                         }
  98                         if (args[argidx] == "-part" && argidx+1 < args.size()) {
  99                                 part = args[++argidx];
 100                                 continue;
 101                         }
 102                         if (args[argidx] == "-run" && argidx+1 < args.size()) {
 103                                 size_t pos = args[argidx+1].find(':');
 104                                 if (pos == std::string::npos)
 105                                         break;
 106                                 run_from = args[++argidx].substr(0, pos);
 107                                 run_to = args[argidx].substr(pos+1);
 108                                 continue;
 109                         }
 110                         if (args[argidx] == "-noflatten") {
 111                                 flatten = false;
 112                                 continue;
 113                         }
 114                         if (args[argidx] == "-retime") {
 115                                 retime = true;
 116                                 continue;
 117                         }
 118                         break;
 119                 }
 120                 extra_args(args, argidx, design);
 121
 122                 if (!design->full_selection())
 123                         log_cmd_error("This command only operates on fully selected designs!\n");
 124
 125                 if (part != "SLG46140V" && part != "SLG46620V" && part != "SLG46621V")
 126                         log_cmd_error("Invalid part name: '%s'\n", part.c_str());
 127
 128                 log_header(design, "Executing SYNTH_GREENPAK4 pass.\n");
 129                 log_push();
 130
 131                 run_script(design, run_from, run_to);
 132
 133                 log_pop();
 134         }
 135
 136         void script() YS_OVERRIDE
 137         {
 138                 if (check_label("begin"))
 139                 {
 140                         run("read_verilog -lib +/greenpak4/cells_sim.v");
 141                         run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 142                 }
 143
 144                 if (flatten && check_label("flatten", "(unless -noflatten)"))
 145                 {
 146                         run("proc");
 147                         run("flatten");
 148                         run("tribuf -logic");
 149                 }
 150
 151                 if (check_label("coarse"))
 152                 {
 153                         run("synth -run coarse");
 154                 }
 155
 156                 if (check_label("fine"))
 157                 {
 158                         run("extract_counter -pout GP_DCMP,GP_DAC -maxwidth 14");
 159                         run("clean");
 160                         run("opt -fast -mux_undef -undriven -fine");
 161                         run("memory_map");
 162                         run("opt -undriven -fine");
 163                         run("techmap");
 164                         run("techmap -map +/greenpak4/cells_latch.v");
 165                         run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
 166                         run("opt -fast");
 167                         if (retime || help_mode)
 168                                 run("abc -dff -D 1", "(only if -retime)");
 169                 }
 170
 171                 if (check_label("map_luts"))
 172                 {
 173                         if (help_mode || part == "SLG46140V") run("nlutmap -assert -luts 0,6,8,2", " (for -part SLG46140V)");
 174                         if (help_mode || part == "SLG46620V") run("nlutmap -assert -luts 2,8,16,2", "(for -part SLG46620V)");
 175                         if (help_mode || part == "SLG46621V") run("nlutmap -assert -luts 2,8,16,2", "(for -part SLG46621V)");
 176                         run("clean");
 177                 }
 178
 179                 if (check_label("map_cells"))
 180                 {
 181                         run("shregmap -tech greenpak4");
 182                         run("dfflibmap -liberty +/greenpak4/gp_dff.lib");
 183                         run("dffinit -ff GP_DFF Q INIT");
 184                         run("dffinit -ff GP_DFFR Q INIT");
 185                         run("dffinit -ff GP_DFFS Q INIT");
 186                         run("dffinit -ff GP_DFFSR Q INIT");
 187                         run("iopadmap -bits -inpad GP_IBUF OUT:IN -outpad GP_OBUF IN:OUT -inoutpad GP_OBUF OUT:IN -toutpad GP_OBUFT OE:IN:OUT -tinoutpad GP_IOBUF OE:OUT:IN:IO");
 188                         run("attrmvcp -attr src -attr LOC t:GP_OBUF t:GP_OBUFT t:GP_IOBUF n:*");
 189                         run("attrmvcp -attr src -attr LOC -driven t:GP_IBUF n:*");
 190                         run("techmap -map +/greenpak4/cells_map.v");
 191                         run("greenpak4_dffinv");
 192                         run("clean");
 193                 }
 194
 195                 if (check_label("check"))
 196                 {
 197                         run("hierarchy -check");
 198                         run("stat");
 199                         run("check -noinit");
 200                 }
 201
 202                 if (check_label("json"))
 203                 {
 204                         if (!json_file.empty() || help_mode)
 205                                 run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
 206                 }
 207         }
 208 } SynthGreenPAK4Pass;
 209
 210 PRIVATE_NAMESPACE_END