techlibs/ice40/arith_map.v

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 (* techmap_celltype = "$alu" *)
  21 module _80_ice40_alu (A, B, CI, BI, X, Y, CO);
  22         parameter A_SIGNED = 0;
  23         parameter B_SIGNED = 0;
  24         parameter A_WIDTH = 1;
  25         parameter B_WIDTH = 1;
  26         parameter Y_WIDTH = 1;
  27
  28         input [A_WIDTH-1:0] A;
  29         input [B_WIDTH-1:0] B;
  30         output [Y_WIDTH-1:0] X, Y;
  31
  32         input CI, BI;
  33         output [Y_WIDTH-1:0] CO;
  34
  35         wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
  36
  37         wire [Y_WIDTH-1:0] A_buf, B_buf;
  38         \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
  39         \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
  40
  41         wire [Y_WIDTH-1:0] AA = A_buf;
  42         wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
  43         wire [Y_WIDTH-1:0] C = {CO, CI};
  44
  45         genvar i;
  46         generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
  47                 SB_CARRY carry (
  48                         .I0(AA[i]),
  49                         .I1(BB[i]),
  50                         .CI(C[i]),
  51                         .CO(CO[i])
  52                 );
  53                 SB_LUT4 #(
  54                         //         I0: 1010 1010 1010 1010
  55                         //         I1: 1100 1100 1100 1100
  56                         //         I2: 1111 0000 1111 0000
  57                         //         I3: 1111 1111 0000 0000
  58                         .LUT_INIT(16'b 0110_1001_1001_0110)
  59                 ) adder (
  60                         .I0(1'b0),
  61                         .I1(AA[i]),
  62                         .I2(BB[i]),
  63                         .I3(C[i]),
  64                         .O(Y[i])
  65                 );
  66         end endgenerate
  67
  68         assign X = AA ^ BB;
  69 endmodule
  70