2 module \$__ICE40_RAM4K (
8 input [15:0] MASK, WDATA
10 parameter integer READ_MODE = 0;
11 parameter integer WRITE_MODE = 0;
12 parameter [0:0] NEGCLK_R = 0;
13 parameter [0:0] NEGCLK_W = 0;
15 parameter [255:0] INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
16 parameter [255:0] INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
17 parameter [255:0] INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
18 parameter [255:0] INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
19 parameter [255:0] INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
20 parameter [255:0] INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
21 parameter [255:0] INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
22 parameter [255:0] INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
23 parameter [255:0] INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
24 parameter [255:0] INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
25 parameter [255:0] INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
26 parameter [255:0] INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
27 parameter [255:0] INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
28 parameter [255:0] INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
29 parameter [255:0] INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
30 parameter [255:0] INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
33 case ({NEGCLK_R, NEGCLK_W})
36 .READ_MODE(READ_MODE),
37 .WRITE_MODE(WRITE_MODE),
69 .READ_MODE(READ_MODE),
70 .WRITE_MODE(WRITE_MODE),
102 .READ_MODE(READ_MODE),
103 .WRITE_MODE(WRITE_MODE),
120 ) _TECHMAP_REPLACE_ (
135 .READ_MODE(READ_MODE),
136 .WRITE_MODE(WRITE_MODE),
153 ) _TECHMAP_REPLACE_ (
171 module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
172 parameter [0:0] CLKPOL2 = 1;
173 parameter [0:0] CLKPOL3 = 1;
175 parameter [4095:0] INIT = 4096'bx;
181 output [15:0] A1DATA;
188 wire [10:0] A1ADDR_11 = A1ADDR;
189 wire [10:0] B1ADDR_11 = B1ADDR;
196 .INIT_0(INIT[ 0*256 +: 256]),
197 .INIT_1(INIT[ 1*256 +: 256]),
198 .INIT_2(INIT[ 2*256 +: 256]),
199 .INIT_3(INIT[ 3*256 +: 256]),
200 .INIT_4(INIT[ 4*256 +: 256]),
201 .INIT_5(INIT[ 5*256 +: 256]),
202 .INIT_6(INIT[ 6*256 +: 256]),
203 .INIT_7(INIT[ 7*256 +: 256]),
204 .INIT_8(INIT[ 8*256 +: 256]),
205 .INIT_9(INIT[ 9*256 +: 256]),
206 .INIT_A(INIT[10*256 +: 256]),
207 .INIT_B(INIT[11*256 +: 256]),
208 .INIT_C(INIT[12*256 +: 256]),
209 .INIT_D(INIT[13*256 +: 256]),
210 .INIT_E(INIT[14*256 +: 256]),
211 .INIT_F(INIT[15*256 +: 256])
212 ) _TECHMAP_REPLACE_ (
227 module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
228 parameter CFG_ABITS = 9;
229 parameter CFG_DBITS = 8;
231 parameter [0:0] CLKPOL2 = 1;
232 parameter [0:0] CLKPOL3 = 1;
234 parameter [4095:0] INIT = 4096'bx;
238 CFG_ABITS == 10 ? 2 :
239 CFG_ABITS == 11 ? 3 : 'bx;
244 input [CFG_ABITS-1:0] A1ADDR;
245 output [CFG_DBITS-1:0] A1DATA;
248 input [CFG_ABITS-1:0] B1ADDR;
249 input [CFG_DBITS-1:0] B1DATA;
252 wire [10:0] A1ADDR_11 = A1ADDR;
253 wire [10:0] B1ADDR_11 = B1ADDR;
255 wire [15:0] A1DATA_16, B1DATA_16;
259 assign A1DATA = {A1DATA_16[14], A1DATA_16[12], A1DATA_16[10], A1DATA_16[ 8],
260 A1DATA_16[ 6], A1DATA_16[ 4], A1DATA_16[ 2], A1DATA_16[ 0]};
261 assign {B1DATA_16[14], B1DATA_16[12], B1DATA_16[10], B1DATA_16[ 8],
262 B1DATA_16[ 6], B1DATA_16[ 4], B1DATA_16[ 2], B1DATA_16[ 0]} = B1DATA;
263 `include "brams_init1.vh"
266 assign A1DATA = {A1DATA_16[13], A1DATA_16[9], A1DATA_16[5], A1DATA_16[1]};
267 assign {B1DATA_16[13], B1DATA_16[9], B1DATA_16[5], B1DATA_16[1]} = B1DATA;
268 `include "brams_init2.vh"
271 assign A1DATA = {A1DATA_16[11], A1DATA_16[3]};
272 assign {B1DATA_16[11], B1DATA_16[3]} = B1DATA;
273 `include "brams_init3.vh"
298 ) _TECHMAP_REPLACE_ (