techlibs/ice40/brams_map.v

   1
   2 module \$__ICE40_RAM4K (
   3         output [15:0] RDATA,
   4         input         RCLK, RCLKE, RE,
   5         input  [10:0] RADDR,
   6         input         WCLK, WCLKE, WE,
   7         input  [10:0] WADDR,
   8         input  [15:0] MASK, WDATA
   9 );
  10         parameter integer READ_MODE = 0;
  11         parameter integer WRITE_MODE = 0;
  12         parameter [0:0] NEGCLK_R = 0;
  13         parameter [0:0] NEGCLK_W = 0;
  14
  15         parameter [255:0] INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  16         parameter [255:0] INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  17         parameter [255:0] INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  18         parameter [255:0] INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  19         parameter [255:0] INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  20         parameter [255:0] INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  21         parameter [255:0] INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  22         parameter [255:0] INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  23         parameter [255:0] INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  24         parameter [255:0] INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  25         parameter [255:0] INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  26         parameter [255:0] INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  27         parameter [255:0] INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  28         parameter [255:0] INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  29         parameter [255:0] INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  30         parameter [255:0] INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
  31
  32         generate
  33                 case ({NEGCLK_R, NEGCLK_W})
  34                         2'b00:
  35                                 SB_RAM40_4K #(
  36                                         .READ_MODE(READ_MODE),
  37                                         .WRITE_MODE(WRITE_MODE),
  38                                         .INIT_0(INIT_0),
  39                                         .INIT_1(INIT_1),
  40                                         .INIT_2(INIT_2),
  41                                         .INIT_3(INIT_3),
  42                                         .INIT_4(INIT_4),
  43                                         .INIT_5(INIT_5),
  44                                         .INIT_6(INIT_6),
  45                                         .INIT_7(INIT_7),
  46                                         .INIT_8(INIT_8),
  47                                         .INIT_9(INIT_9),
  48                                         .INIT_A(INIT_A),
  49                                         .INIT_B(INIT_B),
  50                                         .INIT_C(INIT_C),
  51                                         .INIT_D(INIT_D),
  52                                         .INIT_E(INIT_E),
  53                                         .INIT_F(INIT_F)
  54                                 ) _TECHMAP_REPLACE_ (
  55                                         .RDATA(RDATA),
  56                                         .RCLK (RCLK ),
  57                                         .RCLKE(RCLKE),
  58                                         .RE   (RE   ),
  59                                         .RADDR(RADDR),
  60                                         .WCLK (WCLK ),
  61                                         .WCLKE(WCLKE),
  62                                         .WE   (WE   ),
  63                                         .WADDR(WADDR),
  64                                         .MASK (MASK ),
  65                                         .WDATA(WDATA)
  66                                 );
  67                         2'b01:
  68                                 SB_RAM40_4KNW #(
  69                                         .READ_MODE(READ_MODE),
  70                                         .WRITE_MODE(WRITE_MODE),
  71                                         .INIT_0(INIT_0),
  72                                         .INIT_1(INIT_1),
  73                                         .INIT_2(INIT_2),
  74                                         .INIT_3(INIT_3),
  75                                         .INIT_4(INIT_4),
  76                                         .INIT_5(INIT_5),
  77                                         .INIT_6(INIT_6),
  78                                         .INIT_7(INIT_7),
  79                                         .INIT_8(INIT_8),
  80                                         .INIT_9(INIT_9),
  81                                         .INIT_A(INIT_A),
  82                                         .INIT_B(INIT_B),
  83                                         .INIT_C(INIT_C),
  84                                         .INIT_D(INIT_D),
  85                                         .INIT_E(INIT_E),
  86                                         .INIT_F(INIT_F)
  87                                 ) _TECHMAP_REPLACE_ (
  88                                         .RDATA(RDATA),
  89                                         .RCLK (RCLK ),
  90                                         .RCLKE(RCLKE),
  91                                         .RE   (RE   ),
  92                                         .RADDR(RADDR),
  93                                         .WCLK (WCLK ),
  94                                         .WCLKE(WCLKE),
  95                                         .WE   (WE   ),
  96                                         .WADDR(WADDR),
  97                                         .MASK (MASK ),
  98                                         .WDATA(WDATA)
  99                                 );
 100                         2'b10:
 101                                 SB_RAM40_4KNR #(
 102                                         .READ_MODE(READ_MODE),
 103                                         .WRITE_MODE(WRITE_MODE),
 104                                         .INIT_0(INIT_0),
 105                                         .INIT_1(INIT_1),
 106                                         .INIT_2(INIT_2),
 107                                         .INIT_3(INIT_3),
 108                                         .INIT_4(INIT_4),
 109                                         .INIT_5(INIT_5),
 110                                         .INIT_6(INIT_6),
 111                                         .INIT_7(INIT_7),
 112                                         .INIT_8(INIT_8),
 113                                         .INIT_9(INIT_9),
 114                                         .INIT_A(INIT_A),
 115                                         .INIT_B(INIT_B),
 116                                         .INIT_C(INIT_C),
 117                                         .INIT_D(INIT_D),
 118                                         .INIT_E(INIT_E),
 119                                         .INIT_F(INIT_F)
 120                                 ) _TECHMAP_REPLACE_ (
 121                                         .RDATA(RDATA),
 122                                         .RCLK (RCLK ),
 123                                         .RCLKE(RCLKE),
 124                                         .RE   (RE   ),
 125                                         .RADDR(RADDR),
 126                                         .WCLK (WCLK ),
 127                                         .WCLKE(WCLKE),
 128                                         .WE   (WE   ),
 129                                         .WADDR(WADDR),
 130                                         .MASK (MASK ),
 131                                         .WDATA(WDATA)
 132                                 );
 133                         2'b11:
 134                                 SB_RAM40_4KNRNW #(
 135                                         .READ_MODE(READ_MODE),
 136                                         .WRITE_MODE(WRITE_MODE),
 137                                         .INIT_0(INIT_0),
 138                                         .INIT_1(INIT_1),
 139                                         .INIT_2(INIT_2),
 140                                         .INIT_3(INIT_3),
 141                                         .INIT_4(INIT_4),
 142                                         .INIT_5(INIT_5),
 143                                         .INIT_6(INIT_6),
 144                                         .INIT_7(INIT_7),
 145                                         .INIT_8(INIT_8),
 146                                         .INIT_9(INIT_9),
 147                                         .INIT_A(INIT_A),
 148                                         .INIT_B(INIT_B),
 149                                         .INIT_C(INIT_C),
 150                                         .INIT_D(INIT_D),
 151                                         .INIT_E(INIT_E),
 152                                         .INIT_F(INIT_F)
 153                                 ) _TECHMAP_REPLACE_ (
 154                                         .RDATA(RDATA),
 155                                         .RCLK (RCLK ),
 156                                         .RCLKE(RCLKE),
 157                                         .RE   (RE   ),
 158                                         .RADDR(RADDR),
 159                                         .WCLK (WCLK ),
 160                                         .WCLKE(WCLKE),
 161                                         .WE   (WE   ),
 162                                         .WADDR(WADDR),
 163                                         .MASK (MASK ),
 164                                         .WDATA(WDATA)
 165                                 );
 166                 endcase
 167         endgenerate
 168 endmodule
 169
 170
 171 module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 172         parameter [0:0] CLKPOL2 = 1;
 173         parameter [0:0] CLKPOL3 = 1;
 174
 175         parameter [4095:0] INIT = 4096'bx;
 176
 177         input CLK2;
 178         input CLK3;
 179
 180         input [7:0] A1ADDR;
 181         output [15:0] A1DATA;
 182
 183         input [7:0] B1ADDR;
 184         input [15:0] B1DATA;
 185         input [15:0] B1EN;
 186
 187         wire [10:0] A1ADDR_11 = A1ADDR;
 188         wire [10:0] B1ADDR_11 = B1ADDR;
 189
 190         \$__ICE40_RAM4K #(
 191                 .READ_MODE(0),
 192                 .WRITE_MODE(0),
 193                 .NEGCLK_R(!CLKPOL2),
 194                 .NEGCLK_W(!CLKPOL3),
 195                 .INIT_0(INIT[ 0*256 +: 256]),
 196                 .INIT_1(INIT[ 1*256 +: 256]),
 197                 .INIT_2(INIT[ 2*256 +: 256]),
 198                 .INIT_3(INIT[ 3*256 +: 256]),
 199                 .INIT_4(INIT[ 4*256 +: 256]),
 200                 .INIT_5(INIT[ 5*256 +: 256]),
 201                 .INIT_6(INIT[ 6*256 +: 256]),
 202                 .INIT_7(INIT[ 7*256 +: 256]),
 203                 .INIT_8(INIT[ 8*256 +: 256]),
 204                 .INIT_9(INIT[ 9*256 +: 256]),
 205                 .INIT_A(INIT[10*256 +: 256]),
 206                 .INIT_B(INIT[11*256 +: 256]),
 207                 .INIT_C(INIT[12*256 +: 256]),
 208                 .INIT_D(INIT[13*256 +: 256]),
 209                 .INIT_E(INIT[14*256 +: 256]),
 210                 .INIT_F(INIT[15*256 +: 256])
 211         ) _TECHMAP_REPLACE_ (
 212                 .RDATA(A1DATA),
 213                 .RADDR(A1ADDR_11),
 214                 .RCLK(CLK2),
 215                 .RCLKE(1'b1),
 216                 .RE(1'b1),
 217                 .WDATA(B1DATA),
 218                 .WADDR(B1ADDR_11),
 219                 .MASK(~B1EN),
 220                 .WCLK(CLK3),
 221                 .WCLKE(1'b1),
 222                 .WE(|B1EN)
 223         );
 224 endmodule
 225
 226 module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 227         parameter CFG_ABITS = 9;
 228         parameter CFG_DBITS = 8;
 229
 230         parameter [0:0] CLKPOL2 = 1;
 231         parameter [0:0] CLKPOL3 = 1;
 232
 233         localparam MODE =
 234                 CFG_ABITS ==  9 ? 1 :
 235                 CFG_ABITS == 10 ? 2 :
 236                 CFG_ABITS == 11 ? 3 : 'bx;
 237
 238         input CLK2;
 239         input CLK3;
 240
 241         input [CFG_ABITS-1:0] A1ADDR;
 242         output [CFG_DBITS-1:0] A1DATA;
 243
 244         input [CFG_ABITS-1:0] B1ADDR;
 245         input [CFG_DBITS-1:0] B1DATA;
 246         input B1EN;
 247
 248         wire [10:0] A1ADDR_11 = A1ADDR;
 249         wire [10:0] B1ADDR_11 = B1ADDR;
 250
 251         wire [15:0] A1DATA_16, B1DATA_16;
 252
 253         generate
 254                 if (MODE == 1) begin
 255                         assign A1DATA = {A1DATA_16[14], A1DATA_16[12], A1DATA_16[10], A1DATA_16[ 8],
 256                                          A1DATA_16[ 6], A1DATA_16[ 4], A1DATA_16[ 2], A1DATA_16[ 0]};
 257                         assign {B1DATA_16[14], B1DATA_16[12], B1DATA_16[10], B1DATA_16[ 8],
 258                                 B1DATA_16[ 6], B1DATA_16[ 4], B1DATA_16[ 2], B1DATA_16[ 0]} = B1DATA;
 259                 end
 260                 if (MODE == 2) begin
 261                         assign A1DATA = {A1DATA_16[13], A1DATA_16[9], A1DATA_16[5], A1DATA_16[1]};
 262                         assign {B1DATA_16[13], B1DATA_16[9], B1DATA_16[5], B1DATA_16[1]} = B1DATA;
 263                 end
 264                 if (MODE == 3) begin
 265                         assign A1DATA = {A1DATA_16[11], A1DATA_16[3]};
 266                         assign {B1DATA_16[11], B1DATA_16[3]} = B1DATA;
 267                 end
 268         endgenerate
 269
 270         \$__ICE40_RAM4K #(
 271                 .READ_MODE(MODE),
 272                 .WRITE_MODE(MODE),
 273                 .NEGCLK_R(!CLKPOL2),
 274                 .NEGCLK_W(!CLKPOL3),
 275                 // .INIT_0(INIT[ 0*256 +: 256]),
 276                 // .INIT_1(INIT[ 1*256 +: 256]),
 277                 // .INIT_2(INIT[ 2*256 +: 256]),
 278                 // .INIT_3(INIT[ 3*256 +: 256]),
 279                 // .INIT_4(INIT[ 4*256 +: 256]),
 280                 // .INIT_5(INIT[ 5*256 +: 256]),
 281                 // .INIT_6(INIT[ 6*256 +: 256]),
 282                 // .INIT_7(INIT[ 7*256 +: 256]),
 283                 // .INIT_8(INIT[ 8*256 +: 256]),
 284                 // .INIT_9(INIT[ 9*256 +: 256]),
 285                 // .INIT_A(INIT[10*256 +: 256]),
 286                 // .INIT_B(INIT[11*256 +: 256]),
 287                 // .INIT_C(INIT[12*256 +: 256]),
 288                 // .INIT_D(INIT[13*256 +: 256]),
 289                 // .INIT_E(INIT[14*256 +: 256]),
 290                 // .INIT_F(INIT[15*256 +: 256])
 291         ) _TECHMAP_REPLACE_ (
 292                 .RDATA(A1DATA_16),
 293                 .RADDR(A1ADDR_11),
 294                 .RCLK(CLK2),
 295                 .RCLKE(1'b1),
 296                 .RE(1'b1),
 297                 .WDATA(B1DATA_16),
 298                 .WADDR(B1ADDR_11),
 299                 .WCLK(CLK3),
 300                 .WCLKE(1'b1),
 301                 .WE(|B1EN)
 302         );
 303 endmodule
 304