techlibs/ice40/brams_map.v

   1
   2 module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
   3         parameter [0:0] CLKPOL2 = 1;
   4         parameter [0:0] CLKPOL3 = 1;
   5
   6         input CLK2;
   7         input CLK3;
   8
   9         input [7:0] A1ADDR;
  10         output [15:0] A1DATA;
  11
  12         input [7:0] B1ADDR;
  13         input [15:0] B1DATA;
  14         input [15:0] B1EN;
  15
  16         wire [10:0] A1ADDR_11 = A1ADDR;
  17         wire [10:0] B1ADDR_11 = B1ADDR;
  18
  19         generate
  20                 case ({CLKPOL2, CLKPOL3})
  21                         2'b00:
  22                                 SB_RAM40_4KNRNW #(.WRITE_MODE(0), .READ_MODE(0)) _TECHMAP_REPLACE_ (
  23                                         .RDATA(A1DATA), .RADDR(A1ADDR_11),               .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
  24                                         .WDATA(B1DATA), .WADDR(B1ADDR_11), .WMASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN)
  25                                 );
  26                         2'b01:
  27                                 SB_RAM40_4KNR #(.WRITE_MODE(0), .READ_MODE(0)) _TECHMAP_REPLACE_ (
  28                                         .RDATA(A1DATA), .RADDR(A1ADDR_11),               .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
  29                                         .WDATA(B1DATA), .WADDR(B1ADDR_11), .WMASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN)
  30                                 );
  31                         2'b10:
  32                                 SB_RAM40_4KNW #(.WRITE_MODE(0), .READ_MODE(0)) _TECHMAP_REPLACE_ (
  33                                         .RDATA(A1DATA), .RADDR(A1ADDR_11),               .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
  34                                         .WDATA(B1DATA), .WADDR(B1ADDR_11), .WMASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN)
  35                                 );
  36                         2'b11:
  37                                 SB_RAM40_4K #(.WRITE_MODE(0), .READ_MODE(0)) _TECHMAP_REPLACE_ (
  38                                         .RDATA(A1DATA), .RADDR(A1ADDR_11),               .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
  39                                         .WDATA(B1DATA), .WADDR(B1ADDR_11), .WMASK(B1EN), .WCLK(CLK3), .WCLKE(1'b1), .WE(|B1EN)
  40                                 );
  41                 endcase
  42         endgenerate
  43 endmodule
  44
  45 module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
  46         parameter CFG_ABITS = 9;
  47         parameter CFG_DBITS = 8;
  48
  49         parameter [0:0] CLKPOL2 = 1;
  50         parameter [0:0] CLKPOL3 = 1;
  51
  52         localparam MODE =
  53                 CFG_ABITS ==  9 ? 1 :
  54                 CFG_ABITS == 10 ? 2 :
  55                 CFG_ABITS == 11 ? 3 : 'bx;
  56
  57         input CLK2;
  58         input CLK3;
  59
  60         input [CFG_ABITS-1:0] A1ADDR;
  61         output [CFG_DBITS-1:0] A1DATA;
  62
  63         input [CFG_ABITS-1:0] B1ADDR;
  64         input [CFG_DBITS-1:0] B1DATA;
  65         input B1EN;
  66
  67         wire [10:0] A1ADDR_11 = A1ADDR;
  68         wire [10:0] B1ADDR_11 = B1ADDR;
  69
  70         wire [15:0] A1DATA_16;
  71         wire [15:0] B1DATA_16 = B1DATA;
  72         assign A1DATA = A1DATA_16;
  73
  74         generate
  75                 case ({CLKPOL2, CLKPOL3})
  76                         2'b00:
  77                                 SB_RAM40_4KNRNW #(.WRITE_MODE(MODE), .READ_MODE(MODE)) _TECHMAP_REPLACE_ (
  78                                         .RDATA(A1DATA_16), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
  79                                         .WDATA(B1DATA_16), .WADDR(B1ADDR_11), .WCLK(CLK3), .WCLKE(1'b1), .WE(B1EN)
  80                                 );
  81                         2'b01:
  82                                 SB_RAM40_4KNR #(.WRITE_MODE(MODE), .READ_MODE(MODE)) _TECHMAP_REPLACE_ (
  83                                         .RDATA(A1DATA_16), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
  84                                         .WDATA(B1DATA_16), .WADDR(B1ADDR_11), .WCLK(CLK3), .WCLKE(1'b1), .WE(B1EN)
  85                                 );
  86                         2'b10:
  87                                 SB_RAM40_4RNW #(.WRITE_MODE(MODE), .READ_MODE(MODE)) _TECHMAP_REPLACE_ (
  88                                         .RDATA(A1DATA_16), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
  89                                         .WDATA(B1DATA_16), .WADDR(B1ADDR_11), .WCLK(CLK3), .WCLKE(1'b1), .WE(B1EN)
  90                                 );
  91                         2'b11:
  92                                 SB_RAM40_4K #(.WRITE_MODE(MODE), .READ_MODE(MODE)) _TECHMAP_REPLACE_ (
  93                                         .RDATA(A1DATA_16), .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), .RE(1'b1),
  94                                         .WDATA(B1DATA_16), .WADDR(B1ADDR_11), .WCLK(CLK3), .WCLKE(1'b1), .WE(B1EN)
  95                                 );
  96                 endcase
  97         endgenerate
  98 endmodule
  99